公开(公告)号：US20250166715A1

公开(公告)日：2025-05-22

申请号：US18916863

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyeon Han ,  Jinkyu Kang ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes a plurality of memory cells configured to store at least one bit, the memory device comprising a first wordline and a second wordline. The memory device is configured to perform a first programming operation on the first wordline on a plurality of memory cells in a higher state, the higher state referring to a state in which the plurality of memory cells have threshold voltages above a particular voltage; perform a second programming operation on the second wordline; and perform a third programming operation with a voltage lower than a voltage of the first programming operation when the second programming operation is performed after the first programming operation is performed.

公开(公告)号：US11966625B2

公开(公告)日：2024-04-23

申请号：US17722850

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guyeon Han ,  Sangwon Park ,  Jinkyu Kang ,  Raeyoung Lee ,  Jaeduk Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.