公开(公告)号：US20250088752A1

公开(公告)日：2025-03-13

申请号：US18827047

申请日：2024-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwan JEON ,  Eunji YONG ,  Dongyoung SONG ,  Dongoh KIM ,  Sungsu KIM ,  Yitae KIM ,  Kichrl PARK

IPC: H04N23/71 ,  H04N23/741

Abstract: A method of operating an electronic device includes receiving a plurality of reference code values respectively corresponding to a plurality of reference images captured by an image sensor during different exposure times, receiving a plurality of target code values corresponding to a target image captured by the image sensor, estimating an inverse camera response function (CRF) by adjusting a scale of the plurality of reference code values so that the scale of the plurality of reference code values is equal to a scale of the inverse CRF, wherein the inverse CRF estimates radiance corresponding to the plurality of reference code values, generating a radiance map based on the plurality of reference code values and the inverse CRF, and measuring an effective dynamic range (DR) length of the image sensor based on the radiance map and the plurality of target code values.

公开(公告)号：US20230363100A1

公开(公告)日：2023-11-09

申请号：US18223153

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minwoo CHA ,  Dongoh KIM ,  Dongchan LEE ,  Youngchan LEE ,  Jiseok JUNG ,  Yoongoo HAN

IPC: H05K5/06 ,  G06F1/16 ,  H05K5/00

CPC classification number: H05K5/061 ,  G06F1/1601 ,  H05K5/0017

Abstract: A display apparatus including a sealing member having an improved structure, the display apparatus includes a housing including an opening, a display module including a display panel, the display module arranged inside the housing for the image to be displayed through the opening, a housing cover coupled to the housing to cover the opening while covering a rear surface of the display module, and a sealing member provided to seal a gap between the housing and the housing cover, the sealing member including a contact surface convexly formed toward the housing cover and a first protrusion and a second protrusion arranged on the contact surface, wherein at least a portion of the contact surface located between the first protrusion and the second protrusion is located at a same level as the first protrusion and the second protrusion or protrudes outward of the first protrusion and the second protrusion.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20230354589A1

公开(公告)日：2023-11-02

申请号：US18220323

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108 ,  H01L27/092

CPC classification number: H10B12/50 ,  H01L27/092 ,  H10B12/315

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20220102352A1

公开(公告)日：2022-03-31

申请号：US17241860

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Kyunghwan LEE ,  Dongoh KIM ,  Yongseok KIM ,  Hui-jung KIM ,  Min Hee CHO

IPC: H01L27/108

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

公开(公告)号：US20210408008A1

公开(公告)日：2021-12-30

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L27/24

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20210280992A1

公开(公告)日：2021-09-09

申请号：US17194901

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Jongpil SEO ,  Dongchan LEE ,  Youngchan LEE ,  Jiseok JUNG ,  Minwoo CHA ,  Yoongoo HAN

IPC: H01R4/20 ,  H02G15/013 ,  H01R13/52 ,  H02G3/22

Abstract: A display apparatus including a housing, a display module arranged inside the housing to display an image, a printed circuit board (PCB) connected to a plurality of cables provided to be electrically connected to the display module, a board case having a receiving space formed within the board case, the receiving space accommodating the PCB, and a cable clamp arranged on the board case to close a side of the receiving space, wherein the cable clamp includes a body, a first cut which is cut from a side of the body, a plurality of second cuts branched from an end of the first cut, and a plurality of through holes formed at one ends of the plurality of second cuts and passing through the body, each through hole having one of the plurality of cables inserted to and coupled with the through hole.

公开(公告)号：US20230354590A1

公开(公告)日：2023-11-02

申请号：US18220327

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H10B12/00 ,  H01L27/092

CPC classification number: H10B12/50 ,  H01L27/092 ,  H10B12/315

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20220189969A1

公开(公告)日：2022-06-16

申请号：US17386008

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108 ,  H01L27/092

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20220189967A1

公开(公告)日：2022-06-16

申请号：US17371558

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108

Abstract: A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.