公开(公告)号：US20190393225A1

公开(公告)日：2019-12-26

申请号：US16458292

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-HYUN IM ,  DAEHYUN KIM ,  HOON PARK ,  JAE-HONG SEO ,  CHUNHYUNG CHUNG ,  JAE-JOONG CHOI

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283

Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

公开(公告)号：US20190148383A1

公开(公告)日：2019-05-16

申请号：US16245307

申请日：2019-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  JUN-NOH LEE ,  DONG-HYUN IM ,  YOUNGSEOK KIM ,  KONGSOO LEE

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20190088657A1

公开(公告)日：2019-03-21

申请号：US16050848

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-HYUN IM ,  DAEHYUN KIM ,  HOON PARK ,  JAE-HONG SEO ,  CHUNHYUNG CHUNG ,  JAE-JOONG CHOI

IPC: H01L27/108 ,  H01L21/283 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/10823 ,  H01L21/28026 ,  H01L21/28079 ,  H01L21/283 ,  H01L21/82345 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.