公开(公告)号：US09989856B2

公开(公告)日：2018-06-05

申请号：US15080706

申请日：2016-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Woo Seo ,  Sang-Jin Kim ,  Jong-Seo Hong ,  Jong-Hoon Nah ,  Choon-Ho Song

IPC: G03F7/20 ,  H01L29/66 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: G03F7/2022 ,  G03F7/2002 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.