公开(公告)号：US20230328967A1

公开(公告)日：2023-10-12

申请号：US18067390

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hun NOH ,  Beom Seo KIM ,  Sung Gil KIM

IPC: H10B12/00

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor memory device may include a substrate including an active area defined by an element isolation layer on the substrate, a word line crossing the active area and extending in a first direction, a bit line crossing the active area on the substrate and extending in a second direction, and a bit line contact directly connected to the bit line and the active area. The bit line contact may be between the substrate and the bit line. The bit line contact may include a lower bit line contact directly connected to the active area and an upper bit line contact on and in contact with the lower bit line contact. A width of an upper surface of the lower bit line contact in the second direction may be greater than a width of a lower surface of the upper bit line contact in the second direction.

公开(公告)号：US20230422487A1

公开(公告)日：2023-12-28

申请号：US18149800

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok KIM ,  Jamin KOO ,  Beom Seo KIM ,  Wonseok YOO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.

公开(公告)号：US20230328963A1

公开(公告)日：2023-10-12

申请号：US18062264

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Seo KIM ,  Sung Gil KIM ,  Ji Hun NOH

IPC: H10B12/00

CPC classification number: H01L27/10814

Abstract: A semiconductor memory device including a substrate including an active area defined by an element isolation layer, a bit line extending in a first direction on the substrate, a storage contact on each of both sides of the bit line and connected to the active area, a storage pad on the storage contact and connected to the storage contact and an information storage portion on the storage pad and connected to the storage pad, wherein the storage contact includes a lower storage contact and an upper storage contact on the lower storage contact, at least a portion of the lower storage contact is in the substrate, an entire upper surface of the lower storage contact is in contact with an entire lower surface of the upper storage contact, and each of the lower storage contact and the upper storage contact includes a semiconductor material may be provided.