公开(公告)号：US11362648B2

公开(公告)日：2022-06-14

申请号：US17118082

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aroma Bhat ,  Abdur Rakheeb ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/3562 ,  G01R31/3177 ,  H03K3/027 ,  H03K3/012

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

公开(公告)号：US20210184660A1

公开(公告)日：2021-06-17

申请号：US17118082

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aroma Bhat ,  Abdur Rakheeb ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/3562 ,  G01R31/3177

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

公开(公告)号：US11050424B1

公开(公告)日：2021-06-29

申请号：US16894201

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Sajal Mittal ,  Abdur Rakheeb ,  Nandish Uppal Raravi ,  Vinod Sharma

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/037

Abstract: Methods and apparatus for implementing a current-mirror based level shifter circuit are provided. The current-mirror based level shifter circuit includes a current-mirror circuit, a feedback control circuit, a power down circuit and a plurality of inverter circuits. The apparatus is configured to provide a wide voltage shifting range using the current-mirror based level shifter circuit. The apparatus comprising a feedback loop with two diode connected transistors may provide a constant drivability to the node that drives the output, when a current-mirror circuit is turned-off.