公开(公告)号：US20210273048A1

公开(公告)日：2021-09-02

申请号：US16996282

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJIN PARK ,  CHULKWON PARK ,  SOYEONG KIM ,  EUN A KIM ,  HYO-SUB KIM ,  SOHYUN PARK ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/41

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

公开(公告)号：US20230320076A1

公开(公告)日：2023-10-05

申请号：US17983489

申请日：2022-11-09

Applicant: Samsung Electronics Co., LTD.

Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063

Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

公开(公告)号：US20210296321A1

公开(公告)日：2021-09-23

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INKYOUNG HEO ,  HYO-SUB KIM ,  SOHYUN PARK ,  TAEJIN PARK ,  SEUNG-HEON LEE ,  YOUN-SEOK CHOI ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

公开(公告)号：US20220384449A1

公开(公告)日：2022-12-01

申请号：US17735838

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNJUNG KIM ,  HYO-SUB KIM ,  JAY-BOK CHOI ,  YONGSEOK AHN ,  JUNHYEOK AHN ,  KISEOK LEE ,  MYEONG-DONG LEE ,  YOONYOUNG CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

公开(公告)号：US20210296237A1

公开(公告)日：2021-09-23

申请号：US17097337

申请日：2020-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.