公开(公告)号：US10527901B2

公开(公告)日：2020-01-07

申请号：US15237673

申请日：2016-08-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sangyong No ,  Kwihyun Kim ,  Jiho Moon ,  Keebum Park

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/133 ,  G02F1/1337

Abstract: A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.

公开(公告)号：US20240324389A1

公开(公告)日：2024-09-26

申请号：US18608798

申请日：2024-03-18

Applicant: Samsung Display Co., Ltd.

Inventor： Sunkwun Son ,  Donghee Shin ,  Raeyoung Kim ,  Sangyong No ,  Seungin Baek ,  Yongwoo Lee ,  Sangyun Lim ,  Younho Han

IPC: H10K59/38 ,  H10K59/131

CPC classification number: H10K59/38 ,  H10K59/131

Abstract: A display apparatus includes a power line extending in a first direction, and in a second direction perpendicular to the first direction, and a first sub-pixel having a first pixel electrode, a second sub-pixel having a second pixel electrode, and a third sub-pixel having a third pixel electrode, which display different colors from each other, and which are arranged in a third direction crossing both the first direction and the second direction, in a plan view.

公开(公告)号：US20240054959A1

公开(公告)日：2024-02-15

申请号：US18205901

申请日：2023-06-05

Applicant: Samsung Display Co., Ltd. ,  Konkuk University Industrial Cooperation Corp

Inventor： Kyungho Kim ,  Keechan Park ,  Yikyoung You ,  Sangyong No ,  Gichang Lee ,  Nokyung Park ,  Sunkwun Son ,  Donghee Shin

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0842 ,  G09G2310/0286

Abstract: A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.

公开(公告)号：US10852612B2

公开(公告)日：2020-12-01

申请号：US16733564

申请日：2020-01-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sangyong No ,  Kwihyun Kim ,  Jiho Moon ,  Keebum Park

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/133 ,  G02F1/1337

Abstract: A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.

公开(公告)号：US12190824B2

公开(公告)日：2025-01-07

申请号：US18205901

申请日：2023-06-05

Applicant: Samsung Display Co., Ltd. ,  Konkuk University Industrial Cooperation Corp

Inventor： Kyungho Kim ,  Keechan Park ,  Yikyoung You ,  Sangyong No ,  Gichang Lee ,  Nokyung Park ,  Sunkwun Son ,  Donghee Shin

IPC: G09G3/3266

Abstract: A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.

公开(公告)号：US20250006136A1

公开(公告)日：2025-01-02

申请号：US18626327

申请日：2024-04-04

Applicant: Samsung Display Co., Ltd.

Inventor： Sangyong No ,  Kyungho Kim

IPC: G09G3/3266

Abstract: A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.

公开(公告)号：US20240324287A1

公开(公告)日：2024-09-26

申请号：US18527096

申请日：2023-12-01

Applicant: Samsung Display Co., Ltd.

Inventor： Donghee Shin ,  Sangyong No ,  Sunkwun Son

IPC: H10K59/121 ,  H10K59/131

CPC classification number: H10K59/1213 ,  H10K59/131

Abstract: A display device includes a substrate including a display area in which display elements are arranged, a first subpixel circuit unit in the display area and including a first subpixel circuit, a second subpixel circuit, and a third subpixel circuit, a first scan line extending in a first direction from a side of the first subpixel circuit unit, a second scan line extending in the first direction from another side of the first subpixel circuit unit, a first branch line extending from the first scan line in a second direction crossing the first direction, and a first compensation line extending in the first direction from the first branch line toward the first subpixel circuit adjacent to the second scan line.

公开(公告)号：US20230368736A1

公开(公告)日：2023-11-16

申请号：US18311398

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： Sangyong No ,  Gichang Lee

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2310/0262 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2310/0205 ,  G09G2310/0202 ,  G09G2320/0257 ,  G09G2330/021

Abstract: A pixel including a control transistor electrically connected between a gate of a switching transistor or another switching transistor and a node, and that controls a bias state of a driving transistor according to a voltage of a first gate signal for controlling turn-on of the switching transistor and a voltage of a second gate signal for controlling turn-on of the other switching transistor.

公开(公告)号：US20240321217A1

公开(公告)日：2024-09-26

申请号：US18614544

申请日：2024-03-22

Applicant: Samsung Display Co., Ltd.

Inventor： Kyungho Kim ,  Sangyong No

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0289 ,  G09G2310/08

Abstract: A driving circuit includes stages, each of the stages including: a first control circuit connected to a first voltage input terminal and a second voltage input terminal, and to control voltage levels of a first control node, a second control node, and a third control node; a first output circuit connected to a first clock terminal and a third voltage input terminal, and to output a first output signal according to the voltage levels of the first control node and the second control node; a second output circuit connected to a second clock terminal and the second voltage input terminal, and to output a second output signal according to the voltage levels of the third control node and the second control node; and a boosting circuit connected to a third clock terminal and the second voltage input terminal, and to boost the voltage level of the first control node.

公开(公告)号：US20240321215A1

公开(公告)日：2024-09-26

申请号：US18436904

申请日：2024-02-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kyungho Kim ,  Sangyong No ,  Gichang Lee

IPC: G09G3/3266 ,  G09G3/3233 ,  H03K17/687

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  H03K17/6871 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

Abstract: A stage of a gate driving circuit includes a first control circuit connected to a first voltage input terminal receiving a first voltage and a second voltage input terminal receiving a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node and a second control node; a first output circuit connected to a first clock terminal and a third voltage input terminal receiving a third voltage, the first output circuit being configured to output a gate signal according to the voltage levels of the first control node and the second control node; and a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a carry signal according to the voltage levels of the first control node and the second control node.