公开(公告)号：US20160204135A1

公开(公告)日：2016-07-14

申请号：US14924012

申请日：2015-10-27

Applicant: Samsung Display Co., Ltd.

Inventor： Hyung Min KIM ,  NAM JUNE KIM ,  Jae Hyoung YOUN ,  Jang Soo KIM ,  Se Myung KWON ,  Kang-Young LEE

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  H01L27/32

CPC classification number: H01L27/1225 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78696

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate line disposed on a substrate and including a gate electrode; a gate insulating layer formed on the gate line; a first oxide semiconductor layer disposed on the gate insulating layer and formed of an oxide semiconductor; a data wiring layer disposed on the gate insulating layer and including data line intersecting with the gate line, a source electrode connected to the data line, and a drain electrode facing the drain electrode; and a second oxide semiconductor layer covering the source electrode and the drain electrode, wherein the data wiring layer includes copper or a copper alloy.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极线，设置在基板上并包括栅电极; 栅极绝缘层，形成在栅极线上; 设置在所述栅极绝缘层上并由氧化物半导体形成的第一氧化物半导体层; 配置在所述栅极绝缘层上并且包括与所述栅极线交叉的数据线的数据布线层，与所述数据线连接的源电极以及面对所述漏极的漏电极。 以及覆盖源电极和漏电极的第二氧化物半导体层，其中数据布线层包括铜或铜合金。