公开(公告)号：US10546883B2

公开(公告)日：2020-01-28

申请号：US16160140

申请日：2018-10-15

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Beom Lee ,  Ji-Hoon Shin ,  Ho-Yong Shin

IPC: H01L27/12 ,  G02F1/1362

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

公开(公告)号：US09570481B2

公开(公告)日：2017-02-14

申请号：US14325110

申请日：2014-07-07

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom Lee ,  Sang-Hyun Kang ,  Soo-Chul Kim ,  Hong-Joon Moon ,  Jun-Seok Lee

IPC: H01L37/00 ,  H01L27/12 ,  G02F1/1362 ,  H01L21/768

CPC classification number: H01L27/1259 ,  G02F1/136227 ,  G02F1/136259 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L21/76894 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L2251/568

Abstract: A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.

Abstract translation: 显示基板包括第一开关元件，设置在第一开关元件上的有机层，设置在有机层上的封盖层和覆盖第一发射孔的覆盖电极。 第一开关元件电连接到沿第一方向延伸的栅极线，沿与第一方向交叉的第二方向延伸的数据线和邻近数据线设置的像素电极。 封盖层包括第一发射孔。 覆盖电极与栅极线重叠为第一宽度。 覆盖电极作为第二宽度与第一开关元件重叠。 第二宽度小于第一宽度。

公开(公告)号：US10134776B2

公开(公告)日：2018-11-20

申请号：US14986694

申请日：2016-01-03

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom Lee ,  Ji-Hoon Shin ,  Ho-Yong Shin

IPC: H01L27/12 ,  G02F1/1362

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

公开(公告)号：US09618815B2

公开(公告)日：2017-04-11

申请号：US14694826

申请日：2015-04-23

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Beom Lee ,  Kyoung-Hae Min ,  Yeon-Ha Baek ,  Ji-Hoon Shin ,  Ho-Yong Shin ,  Jae-Hyun Lee

IPC: G02F1/1362 ,  H01L27/12 ,  H01L21/768 ,  G09G3/20 ,  G09G3/36 ,  G02F1/13 ,  H01L21/66 ,  H01L21/48

CPC classification number: G02F1/136259 ,  G02F1/1309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136222 ,  G02F2001/136263 ,  G02F2201/42 ,  G09G3/20 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2330/08 ,  G09G2330/12 ,  H01L21/485 ,  H01L21/76894 ,  H01L22/22 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L2221/101

Abstract: A display substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, an organic layer disposed on the data metal pattern, a repair hole penetrating the organic layer and exposing a crossing area in which the gate line crosses with the data line and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

公开(公告)号：US09837035B2

公开(公告)日：2017-12-05

申请号：US14636965

申请日：2015-03-03

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Beom Lee ,  Jun-Seok Lee

IPC: G06F3/038 ,  G09G3/36

CPC classification number: G09G3/3666 ,  G09G2300/0426 ,  G09G2300/0478 ,  G09G2320/0247

Abstract: A liquid crystal display including a display panel having data link lines, data lines, scan lines, and pixels connected to the data lines and the scan lines, a source drive integrated circuit configured to supply data voltages to the data lines via the data link lines, and a scan driver configured to provide scan signals to the scan lines. A p-th (p is a positive integer) data link line is connected to a (p+1)-th data line, and a (p+1)-th data link line is connected to a p-th data line.

公开(公告)号：US09831138B2

公开(公告)日：2017-11-28

申请号：US14290064

申请日：2014-05-29

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom Lee ,  Sang-Hyun Kang ,  Soo-Chul Kim ,  Hong-Joon Moon ,  Jun-Seok Lee

IPC: H01L21/66 ,  G01R31/26 ,  H01L27/12 ,  G09G3/00 ,  G09G3/36

CPC classification number: H01L22/32 ,  G09G3/006 ,  G09G3/3614 ,  G09G2300/0426

Abstract: A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.