公开(公告)号：US09634037B2

公开(公告)日：2017-04-25

申请号：US14698341

申请日：2015-04-28

Applicant: Samsung Display Co. Ltd.

Inventor： Jong Hyun Choung ,  Bong Kyun Kim

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  H01L27/124 ,  H01L29/78696

Abstract: An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate lines that extend along a first direction; and a data line that is formed by connecting a plurality of first sub-data lines extending along a second direction and a plurality of second sub-data lines extending along a third direction, wherein the gate lines overlap the second sub-data lines with an insulating layer interposed therebetween.

公开(公告)号：US10564549B2

公开(公告)日：2020-02-18

申请号：US15692437

申请日：2017-08-31

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Beung Hwa Jeong ,  Jong Hyun Choung ,  Sung Chul Kim

IPC: G03F7/42 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/47 ,  H01L21/033 ,  H01L21/311

Abstract: A method of forming a thin film pattern includes providing a thin film on a substrate, providing a photoresist on the thin film, forming a first photoresist pattern having a first packing density by exposing and developing the photoresist, etching the thin film by using the first photoresist pattern as a mask, processing the first photoresist pattern to convert the first photoresist pattern into a second photoresist pattern having a second packing density, which is lower than the first packing density, and stripping the second photoresist pattern by spraying steam onto the second photoresist pattern.

公开(公告)号：US12274093B2

公开(公告)日：2025-04-08

申请号：US17672249

申请日：2022-02-15

Applicant: Samsung Display Co., LTD.

Inventor： Joon Yong Park ,  Gyung Min Baek ,  Shin Il Choi ,  Do Keun Song ,  Young Rok Kim ,  Jong Hyun Choung

IPC: H01L27/12 ,  H01L23/00 ,  H01L25/16 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60

Abstract: A display device includes conductive layers including wires and conductive patterns in a display area and a pad area, a via layer on the conductive layers, a first electrode and a second electrode on the via layer in the display area and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, light emitting elements on the first electrode and the second electrode spaced apart from each other on the first insulating layer, and a first connection electrode on the first electrode and electrically contacting the light emitting elements, and a second connection electrode on the second electrode and electrically contacting the light emitting elements, each of the conductive layers includes a first metal layer and a second metal layer on the first metal layer, and the second metal layer contains copper and has a grain size of about 155 nm or less.

公开(公告)号：US11652111B2

公开(公告)日：2023-05-16

申请号：US17462803

申请日：2021-08-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong Hyun Choung ,  Jae Uoon Kim ,  Hyun Ah Sung

IPC: H01L27/12 ,  H01L25/16 ,  H01L27/32

CPC classification number: H01L27/1244 ,  H01L27/1259 ,  H01L25/167 ,  H01L27/1248 ,  H01L27/3276

Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.

公开(公告)号：US11557614B2

公开(公告)日：2023-01-17

申请号：US17003524

申请日：2020-08-26

Applicant: Samsung Display Co., LTD.

Inventor： Jae Uoon Kim ,  Hong Sick Park ,  Jong Hyun Choung

IPC: H01L27/12 ,  H01L27/32 ,  H01L21/4763

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

公开(公告)号：US10825844B2

公开(公告)日：2020-11-03

申请号：US16424388

申请日：2019-05-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hyun Choung ,  Jae Uoon Kim

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.

公开(公告)号：US20200243563A1

公开(公告)日：2020-07-30

申请号：US16424388

申请日：2019-05-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hyun Choung ,  Jae Uoon KIM

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.

公开(公告)号：US12041830B2

公开(公告)日：2024-07-16

申请号：US18084274

申请日：2022-12-19

Applicant: Samsung Display Co., LTD.

Inventor： Jae Uoon Kim ,  Hong Sick Park ,  Jong Hyun Choung

IPC: H10K59/131 ,  H01L27/12 ,  H10K59/123 ,  H01L21/4763 ,  H10K59/38

CPC classification number: H10K59/131 ,  H01L27/124 ,  H01L27/1259 ,  H10K59/123 ,  H01L21/47635 ,  H01L27/1225 ,  H10K59/38

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

公开(公告)号：US10128383B2

公开(公告)日：2018-11-13

申请号：US14986716

申请日：2016-01-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hyun Choung

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417

Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.