公开(公告)号：US20220166415A1

公开(公告)日：2022-05-26

申请号：US17524306

申请日：2021-11-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Michel Cuenca ,  Ludovic Girardeau

IPC: H03K4/50 ,  H03K3/037 ,  H03K5/24

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

公开(公告)号：US10860049B2

公开(公告)日：2020-12-08

申请号：US16594405

申请日：2019-10-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Regis Roubadia ,  Ludovic Girardeau

IPC: H04W4/40 ,  G06F1/025 ,  H03K19/0185

Abstract: A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

公开(公告)号：US11581880B2

公开(公告)日：2023-02-14

申请号：US17524306

申请日：2021-11-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Michel Cuenca ,  Ludovic Girardeau

IPC: H03K4/50 ,  H03K5/24

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.