公开(公告)号：US20250125293A1

公开(公告)日：2025-04-17

申请号：US18789098

申请日：2024-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.

公开(公告)号：US20250079403A1

公开(公告)日：2025-03-06

申请号：US18666556

申请日：2024-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, the first semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of conductive patterns on the active surface of each second semiconductor substrate of the plurality of second semiconductor chips, and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and on the inactive surface of each second semiconductor substrate of the plurality of second semiconductor chips, where the plurality of bonding pads are respectively connected to the plurality of conductive patterns.

公开(公告)号：US20240429198A1

公开(公告)日：2024-12-26

申请号：US18753612

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H10B80/00

Abstract: A method of manufacturing a semiconductor package according to embodiments of the present disclosure has an effect of reducing the size of the semiconductor package by minimizing a distance between semiconductor chips by self-aligning the semiconductor chips on pads having fine gaps due to the surface tension of solder bumps.

公开(公告)号：US20240421016A1

公开(公告)日：2024-12-19

申请号：US18667269

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Jing Cheng LIN ,  Jihwan SUH ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first molding layer, a dummy chip and a second molding layer. Each second semiconductor chip includes a semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface. The first molding layer surrounds a portion of an upper surface of the first semiconductor chip and side surfaces of the second semiconductor chips and includes a trench that extends from an upper surface of the first molding layer into the first molding layer. The dummy chip is stacked on an uppermost second semiconductor chip of the second semiconductor chips. The second molding layer surrounds side surfaces of the dummy chip, and covers the first molding layer.

公开(公告)号：US20230074933A1

公开(公告)日：2023-03-09

申请号：US17728727

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkun JEE ,  Unbyoung KANG ,  Sanghoon LEE ,  Chungsun LEE

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

公开(公告)号：US20250014974A1

公开(公告)日：2025-01-09

申请号：US18750209

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A method includes: forming a seed layer; forming a first photoresist pattern on the seed layer; forming a metal pad on the seed layer by using the first photoresist pattern; forming a second photoresist pattern on the seed layer; forming a conductive post on the seed layer by using the second photoresist pattern; providing, on the metal pad, a first semiconductor chip on which a conductive pillar and an insulating material layer surrounding a sidewall of the conductive pillar are formed; bonding the first semiconductor chip to the metal pad by using a connection terminal; forming a first molding layer surrounding the first semiconductor chip; removing the connection terminal and the metal pad; and forming a redistribution structure connected to the conductive pillar.

公开(公告)号：US20250006618A1

公开(公告)日：2025-01-02

申请号：US18634101

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: Provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.

公开(公告)号：US20240429200A1

公开(公告)日：2024-12-26

申请号：US18665102

申请日：2024-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a redistribution structure including: a passivation layer; an under bump metallurgy (UBM) layer on a portion of a lower surface of the passivation layer; and a conductive layer in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer. The semiconductor package further includes: a bridge chip on the redistribution structure and including a bridge chip pad; a first molding layer sealing the bridge chip on the redistribution structure; conductive posts spaced apart from each other in a horizontal direction within the first molding layer, the bridge chip being between the conductive posts and each of the conductive posts; and a semiconductor chips on the first molding layer and the bridge chip, each of the semiconductor chips including a chip pad and a solder bump.

公开(公告)号：US20250079365A1

公开(公告)日：2025-03-06

申请号：US18667796

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip hybrid-bonded to the first semiconductor chip. The first semiconductor chip includes first main pads, which are apart from each other, and a first bonding insulation layer extending around the first main pads. Each of the first main pads includes first sub main pads apart from each other. The second semiconductor chip includes second main pads, which are spaced apart from each other, and a second bonding insulation layer extending around the second main pads. The second main pads are aligned with the first main pads. Each of the second main pads includes second sub main pads spaced apart from each other. Each of the second sub main pads is bonded to a respective one of the first sub main pads. The second bonding insulation layer is bonded to the first bonding insulation layer.

公开(公告)号：US20240429203A1

公开(公告)日：2024-12-26

申请号：US18427470

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a plurality of semiconductor chips on an upper surface of the second redistribution structure, a bridge chip on a lower surface of the second redistribution structure, and a first molding layer between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip, wherein the first molding layer is between the bridge chip and the first redistribution structure.