公开(公告)号：US20200343219A1

公开(公告)日：2020-10-29

申请号：US16923418

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-hoon KIM ,  Kil-soo KIM ,  Kyung-suk OH ,  Tae-joo HWANG

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/367 ,  H04M1/02

Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

公开(公告)号：US20160300806A1

公开(公告)日：2016-10-13

申请号：US14978550

申请日：2015-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon KIM ,  Keung-beum KIM

IPC: H01L23/00

CPC classification number: H01L23/291 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73259 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/014

Abstract: Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on the one surface of the semiconductor chip. The redistribution structure includes a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer. The redistribution insulating layer includes a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant. The first insulating portion and the second insulating portion are connected to each other in a horizontal direction.

Abstract translation: 提供了一种半导体封装，其包括其上形成有芯片焊盘的一个表面的半导体芯片和形成在半导体芯片的一个表面上的再分布结构。 再分配结构包括连接到芯片焊盘的再分配层和插入在半导体芯片和再分布层之间的再分布绝缘层。 再分布绝缘层包括具有第一介电常数的第一绝缘部分和具有不同于第一介电常数的第二介电常数的第二绝缘部分。 第一绝缘部分和第二绝缘部分在水平方向上彼此连接。

公开(公告)号：US20180138225A1

公开(公告)日：2018-05-17

申请号：US15797375

申请日：2017-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-hoon KIM ,  Ji-chul KIM ,  Seung-yong CHA ,  Jae-choon KIM

IPC: H01L27/146 ,  H01L23/34 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L27/14634 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/345 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2224/18 ,  H04N5/378

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

公开(公告)号：US20190295917A1

公开(公告)日：2019-09-26

申请号：US16190825

申请日：2018-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kil-soo KIM ,  Yong-hoon KIM ,  Hyun-ki KIM ,  Kyung-suk OH

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

公开(公告)号：US20190148337A1

公开(公告)日：2019-05-16

申请号：US16002018

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon KIM ,  Kil-soo KIM ,  Kyung-suk OH ,  Tae-joo HWANG

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/367

Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

公开(公告)号：US20180158830A1

公开(公告)日：2018-06-07

申请号：US15593965

申请日：2017-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-hoon KIM

IPC: H01L27/11

CPC classification number: H01L27/118 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11286 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor' device may include: a substrate; a first well region formed on the substrate; a second well region formed on the substrate, the first well region and the second well region extending in a first direction and being adjacent to each other in a second direction crossing the first direction; a first active region formed in the first well region; a first power region formed in the first well region, the first active region and the first power region being separate from each other in the first direction; a second active region array formed in the second well region; a second power region formed in the second well region, the second active region array and the second power region being separate from each other in the first direction; and a first dummy active region formed in the first well region between the first active region and the first power region, the first dummy active region being separate from the first active region and the first power region in the first direction.