公开(公告)号：US20150311298A1

公开(公告)日：2015-10-29

申请号：US14740476

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L29/423 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US09082653B2

公开(公告)日：2015-07-14

申请号：US14561788

申请日：2014-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/788 ,  H01L23/52 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US09245899B2

公开(公告)日：2016-01-26

申请号：US14740476

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US20150084109A1

公开(公告)日：2015-03-26

申请号：US14561788

申请日：2014-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract translation: 半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口， 剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。