公开(公告)号：US20240177750A1

公开(公告)日：2024-05-30

申请号：US18144531

申请日：2023-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkon JO ,  Gyesik OH ,  Wangyong IM ,  Duk Sung KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1096 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1093

Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.