公开(公告)号：US20240347597A1

公开(公告)日：2024-10-17

申请号：US18517893

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINWOO LEE ,  YOUNGKYOU SHIN ,  SUTAE KIM

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, a first semiconductor pattern on the active pattern, and gate electrodes extending in a first direction and arranged in a second direction intersecting the first direction. A first top surface of the first semiconductor pattern includes first and second corners spaced apart from each other in the first direction. The first top surface of the first semiconductor pattern includes a first portion connecting the first and second corners. A length of the first portion of the first semiconductor pattern is greater than a distance in the first direction between the first corner and the second corner.

公开(公告)号：US20230079697A1

公开(公告)日：2023-03-16

申请号：US17868401

申请日：2022-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO LEE ,  YUNSE OH ,  BYUNG-SUNG KIM ,  SUTAE KIM ,  Seung CHOI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: a substrate including a first active pattern separated into a pair of first active patterns by a trench; a device isolation layer filling the trench; first source/drain patterns on the first active pattern; a first channel pattern connected to the first source/drain patterns and including semiconductor patterns; a first dummy gate electrode that extends while being adjacent to a first sidewall of the trench; a gate electrode that is spaced apart in the first direction from the first dummy gate electrode and extends while running across the first channel pattern, a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending between the gate electrode and the first dummy gate electrode. A top surface of the separation pattern is at a same level as that of the gate capping pattern.