公开(公告)号：US20220208673A1

公开(公告)日：2022-06-30

申请号：US17344670

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM ,  WANDON KIM ,  SEOWOO NAM ,  SUNYOUNG NOH ,  KI CHUL PARK ,  JONGCHAN SHIN ,  MINJOO LEE ,  HYUNBAE LEE ,  SEUNGSEOK HA

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

公开(公告)号：US20250118669A1

公开(公告)日：2025-04-10

申请号：US18630670

申请日：2024-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUI BOK LEE ,  RAKHWAN KIM

IPC: H01L23/528 ,  H01L29/423

Abstract: A semiconductor device comprising: first conductive lines spaced apart from each other; and a conductive structure in contact with upper surfaces of the first conductive lines, wherein the conductive structure includes a lower portion of the conductive structure and an upper portion of the conductive structure, wherein the lower portion of the conductive structure is in contact with the upper surfaces of the first conductive lines, wherein the upper portion of the conductive structure is on the lower portion of the conductive structure, wherein a width of the lower portion of the conductive structure decreases as a distance between the lower portion of the conductive structure and the upper surfaces of the first conductive lines decreases, and wherein a width of the upper portion of the conductive structure increases as a distance between the upper portion of the conductive structures and the upper surfaces of the first conductive lines decreases.

公开(公告)号：US20230022545A1

公开(公告)日：2023-01-26

申请号：US17680507

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUI BOK LEE ,  WANDON KIM ,  RAKHWAN KIM

IPC: H01L23/522 ,  H01L29/417 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.