公开(公告)号：US20220115369A1

公开(公告)日：2022-04-14

申请号：US17559152

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu RYU ,  Min-Su KIM ,  Yong-Geol KIM ,  Dae-Seong LEE

IPC: H01L27/02 ,  H01L23/552 ,  G03F1/36 ,  H01L27/118 ,  G06F30/398

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

公开(公告)号：US20190393205A1

公开(公告)日：2019-12-26

申请号：US16250000

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Seong LEE ,  Ah-Reum KIM ,  Min-Su KIM ,  Jong-Kyu RYU

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L23/50

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

公开(公告)号：US20150349756A1

公开(公告)日：2015-12-03

申请号：US14824302

申请日：2015-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee KIM ,  Min-Su KIM ,  Ji-Kyum KIM ,  Emil KAGRAMANYAN ,  Dae-Seong LEE ,  Gun-Ok JUNG ,  Uk-Rae CHO

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。

公开(公告)号：US20190214377A1

公开(公告)日：2019-07-11

申请号：US16105165

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu RYU ,  Min-Su KIM ,  Yong-Geol KIM ,  Dae-Seong LEE

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/552 ,  H01L27/118 ,  G03F1/36

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5081 ,  H01L23/552 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2027/11892

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

公开(公告)号：US20140368246A1

公开(公告)日：2014-12-18

申请号：US14295802

申请日：2014-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee KIM ,  Min-Su KIM ,  Ji-Kyum KIM ,  Emil KAGRAMANYAN ,  Dae-Seong LEE ,  Gun-Ok JUNG ,  Uk-Rae CHO

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。