公开(公告)号：US20250157524A1

公开(公告)日：2025-05-15

申请号：US18754855

申请日：2024-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung LEE ,  CHULKWON PARK ,  DONGHAK SHIN

IPC: G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a first chip including a cell area and a remaining area, the cell area including a plurality of memory cells; and a second chip including a core area corresponding to the cell area and a peripheral area corresponding to the remaining area, the first chip and the second chip overlap along a vertical direction. Core circuits are provided in the core area of the second chip and peripheral circuits are provided in the peripheral area of the second chip. The core circuits and the peripheral circuits are configured to control operation of the plurality of memory cells, and passive elements connected to the peripheral circuits of the second chip are provided in the remaining area of the first chip.

公开(公告)号：US20250126810A1

公开(公告)日：2025-04-17

申请号：US18734650

申请日：2024-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung LEE ,  Sanghoon Jung ,  Youngseok Park ,  Changsik Yoo

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

Abstract: A memory device is provided. The memory device includes: a plurality of sub-array regions arranged spaced apart in a first and second horizontal directions, and each sub-array region including a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region including a first metal pattern extending in the first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

公开(公告)号：US20250061938A1

公开(公告)日：2025-02-20

申请号：US18421152

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung LEE ,  Young Seok PARK

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C29/52

Abstract: A memory device includes a memory cell array including memory cells, a single-ended bitline sense amplifier connected to the memory cells through a bitline and a complementary bitline, and electrically connected through one of the bitline or the complementary bitline in response to the memory cells being activated. A DSI circuit is configured to conditionally transmit complementary input data generated by inverting input data to the single-ended bitline sense amplifier in response to a first number of bits included in the input data having a first level greater than a second number of bits included in the input data having a second level, and a data inversion flag indicating that the input data is inverted, to the sense amplifier. The sense amplifier stores the complementary input data in the memory cell array and the data inversion flag in a specified partial area of the memory cell array.