公开(公告)号：US20240387648A1

公开(公告)日：2024-11-21

申请号：US18616917

申请日：2024-03-26

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Tomoya NISHIMURA

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423

Abstract: Performance of a semiconductor device is improved. In a semiconductor substrate (SUB), a trench TR1 and a trench TR2 are formed so as to reach a predetermined depth from an upper surface (TS) of the semiconductor substrate (SUB). A field-plate electrode (FP) is formed at a lower portion of the trench TR1, and a gate-electrode GE1 is formed at an upper portion of the trench TR1. A gate electrode GE2 is formed inside the trench TR2. The depth of the trench TR1 is deeper than the depth of the trench TR2. The trench TR1 is surrounded by the trench TR2 in plan view.

公开(公告)号：US20240113218A1

公开(公告)日：2024-04-04

申请号：US18353250

申请日：2023-07-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya NISHIMURA ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A first trench extending in a Y direction is formed in each of a semiconductor substrate located in a cell region and the semiconductor substrate located in an outer peripheral region. A second trench is formed in the semiconductor substrate in the outer peripheral region so as to surround the cell region in a plan view. A p-type body region is formed in the semiconductor substrate in each region. A plurality of p-type floating regions is formed in the semiconductor substrate in the outer peripheral region. A field plate electrode is formed at a lower portion of each of the first trench and the second trench. A gate electrode is formed at an upper portion of the first trench located in the cell region. A floating gate electrode is formed at an upper portion of each of the first trench located in the outer peripheral region and the second trench.