公开(公告)号：US11959962B2

公开(公告)日：2024-04-16

申请号：US17808357

申请日：2022-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chengyue Yu ,  Hua Guan ,  Yingjie Chen ,  Fan Yang ,  Yufei Pan ,  Jize Jiang ,  Shamim Ahmed

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G01R31/2891

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

公开(公告)号：US11803204B2

公开(公告)日：2023-10-31

申请号：US17239377

申请日：2021-04-23

Applicant: QUALCOMM Incorporated

Inventor： Xiaodong Meng ,  Fan Yang ,  Yufei Pan ,  Hua Guan ,  Kuan Chuang Koay ,  Jize Jiang

IPC: G05F1/59 ,  G05F1/575 ,  H04B1/40

CPC classification number: G05F1/59 ,  G05F1/575 ,  H04B1/40

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.