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    LOW LATENCY TRANSMISSION SYSTEMS AND METHODS FOR LONG DISTANCES IN SOUNDWIRE SYSTEMS
    1.
    发明申请
    LOW LATENCY TRANSMISSION SYSTEMS AND METHODS FOR LONG DISTANCES IN SOUNDWIRE SYSTEMS 有权
    低频延迟传输系统及其在线系统中长距离的方法

    公开(公告)号：US20160337741A1

    公开(公告)日：2016-11-17

    申请号：US15145089

    申请日：2016-05-03

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Terrence Brian Remple

    IPC: H04R1/10 ,  G06F3/16 ,  H04R3/12 ,  H04B1/3827 ,  H04R3/00

    CPC classification number: H04R1/1033 ,  G06F3/162 ,  G06F13/4045 ,  H04B1/3833 ,  H04R3/005 ,  H04R3/12

    Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

    Abstract translation: 公开了在SOUNDWIRE系统中用于长距离的低延迟传输系统和方法。 在示例性方面，SOUNDWIRE子系统通过桥耦合到长电缆。 桥将SOUNDWIRE信号转换成信号以通过长电缆传输，并将信号从长电缆转换为SOUNDWIRE信号，以在SOUNDWIRE子系统中传输。 信号类型之间的转换可以包括将类似类型的信号连接成通过长电缆串行传输的组。 以这种方式连接位插槽在总线周转中消耗最少的开销，从而减少延迟。 在另外的方面，桥接器的功能可以并入耳机或移动终端。

    APPARATUSES, METHODS, AND SYSTEMS FOR ENABLING HIGHER CURRENT CHARGING OF UNIVERSAL SERIAL BUS (USB) SPECIFICATION REVISION 2.0 (USB 2.0) PORTABLE ELECTRONIC DEVICES FROM USB 3.X HOSTS
    2.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR ENABLING HIGHER CURRENT CHARGING OF UNIVERSAL SERIAL BUS (USB) SPECIFICATION REVISION 2.0 (USB 2.0) PORTABLE ELECTRONIC DEVICES FROM USB 3.X HOSTS 审中-公开
    USB 3.0规格说明版本2.0（USB 2.0）便携式电子设备从USB 3.X主机启用更高电流充电的装置，方法和系统

    公开(公告)号：US20160028250A1

    公开(公告)日：2016-01-28

    申请号：US14444443

    申请日：2014-07-28

    Applicant: QUALCOMM Incorporated

    Inventor： Devdutt Patnaik ,  Jay Yu Jae Choi ,  Terrence Brian Remple

    IPC: H02J7/00 ,  G06F11/22 ,  G06F11/30

    CPC classification number: H02J7/007 ,  G06F1/266 ,  G06F13/4282 ,  G06F2213/0042 ,  H02J7/0004 ,  H02J7/0052 ,  H02J2007/0062

    Abstract: Apparatuses, methods, and systems for enabling higher current charging of Universal Serial Bus (USB) Specification Revision 2.0 (USB 2.0) portable electronic devices from USB 3.x hosts are disclosed. In one aspect, a USB 2.0 controller is provided in a USB 2.0 portable device. A USB 3.x controller is provided in a USB 3.x host. The USB 2.0 controller is configured to draw a higher charging current than specified in USB 2.0 for the USB 2.0 portable device over a USB 2.0 cable. In order to draw the higher charging current without violating USB 2.0, the USB 2.0 controller is configured to use one or more reserved elements in an existing USB 2.0 descriptor(s) or bitmap(s) to indicate a higher charging current request from the USB 2.0 controller.

    Abstract translation: 公开了用于实现USB 3.x主机的通用串行总线（USB）规范2.0版（USB 2.0）便携式电子设备的更高电流充电的装置，方法和系统。 一方面，在USB 2.0便携式设备中提供USB 2.0控制器。 USB 3.x主机中提供USB 3.x控制器。 USB 2.0控制器配置为通过USB 2.0电缆为USB 2.0便携式设备绘制比USB 2.0中规定的更高的充电电流。 为了在不违反USB 2.0的情况下绘制更高的充电电流，USB 2.0控制器被配置为使用现有USB 2.0描述符或位图中的一个或多个保留元素来指示来自USB的更高的充电电流请求 2.0控制器。

    USING USB SIGNALING TO TRIGGER A DEVICE TO ENTER A MODE OF OPERATION
    3.
    发明申请
    USING USB SIGNALING TO TRIGGER A DEVICE TO ENTER A MODE OF OPERATION 有权
    使用USB信号触发设备进入操作模式

    公开(公告)号：US20150032909A1

    公开(公告)日：2015-01-29

    申请号：US14337904

    申请日：2014-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Devdutt Patnaik ,  Jay Yu Jae Choi ,  Yanru Li

    IPC: G06F13/38

    CPC classification number: G06F13/385 ,  G06F13/4291

    Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

    Abstract translation: 提供了一种在通用串行总线（USB）兼容客户端设备中触发所需操作模式的方法。 USB兼容的客户端设备通过USB总线检测到它已经耦合到与USB兼容的主机设备。 USB兼容客户端设备尝试将USB总线的数据线拉高。 USB兼容的客户端设备然后确定数据线保持拉低，从而指示USB兼容的客户端设备应该进入第一操作模式。 USB兼容客户端设备根据第一种操作模式进行操作。

    Systems and methods for power conservation in a phase locked loop (PLL)
    5.
    发明授权
    Systems and methods for power conservation in a phase locked loop (PLL) 有权

    公开(公告)号：US10727838B2

    公开(公告)日：2020-07-28

    申请号：US16035024

    申请日：2018-07-13

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Ilker Deligoz

    IPC: H03L7/07 ,  G06F1/10 ,  H03L7/08 ,  H03L7/099

    Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

    Using USB signaling to trigger a device to enter a mode of operation
    8.
    发明授权
    Using USB signaling to trigger a device to enter a mode of operation 有权
    使用USB信号触发设备进入操作模式

    公开(公告)号：US09418033B2

    公开(公告)日：2016-08-16

    申请号：US14337904

    申请日：2014-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Devdutt Patnaik ,  Jay Yu Jae Choi ,  Yanru Li

    IPC: G06F3/00 ,  G06F13/38 ,  G06F13/42

    CPC classification number: G06F13/385 ,  G06F13/4291

    Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

    Abstract translation: 提供了一种在通用串行总线（USB）兼容客户端设备中触发所需操作模式的方法。 USB兼容的客户端设备通过USB总线检测到它已经耦合到与USB兼容的主机设备。 USB兼容客户端设备尝试将USB总线的数据线拉高。 USB兼容的客户端设备然后确定数据线保持拉低，从而指示USB兼容的客户端设备应该进入第一操作模式。 USB兼容客户端设备根据第一种操作模式进行操作。

    SYSTEMS AND METHODS FOR CONSERVING POWER IN A UNIVERSAL SERIAL BUS (USB)
    9.
    发明申请
    SYSTEMS AND METHODS FOR CONSERVING POWER IN A UNIVERSAL SERIAL BUS (USB) 审中-公开
    在通用串行总线（USB）中保存电源的系统和方法

    公开(公告)号：US20150378418A1

    公开(公告)日：2015-12-31

    申请号：US14315985

    申请日：2014-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Nir Gerber ,  Terrence Brian Remple ,  Russell Coleman Deans ,  Moshe Ben Shoshan ,  Glenn Aaron Murphy

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/325 ,  G06F1/3253 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D50/20

    Abstract: Systems and methods for conserving power in a universal serial bus (USB) are disclosed. In one aspect, when a USB device enters a low power mode (e.g., U1 or U2), a clock associated with the USB device is modified to also enter a low power mode. Since the PIPE interface associated with the USB device still requires a clock signal, the low power clock mode must still be able to provide the PIPE interface with a clock signal. However, the clock signal to the PIPE interface does not need to be the same frequency or accuracy as the clock signal used by the USB interface. The modification to the clock changes the clock frequency to a low frequency compared to the normal clock frequency. By using a low frequency clock for the PIPE interface, power is conserved while preserving the functionality of the PIPE interface.

    Abstract translation: 公开了在通用串行总线（USB）中节省功率的系统和方法。 一方面，当USB设备进入低功率模式（例如，U1或U2）时，与USB设备关联的时钟被修改为也进入低功率模式。 由于与USB设备相关联的PIPE接口仍然需要时钟信号，所以低功耗时钟模式仍然能够为PIPE接口提供时钟信号。 然而，到PIPE接口的时钟信号不需要与USB接口使用的时钟信号相同的频率或精度。 与正常时钟频率相比，时钟的修改将时钟频率更改为低频。 通过为PIPE接口使用低频时钟，节省功率，同时保持PIPE接口的功能。

    SYSTEMS AND METHODS FOR POWER CONSERVATION IN A PHASE LOCKED LOOP (PLL)
    10.
    发明申请
    SYSTEMS AND METHODS FOR POWER CONSERVATION IN A PHASE LOCKED LOOP (PLL) 审中-公开

    公开(公告)号：US20200021295A1

    公开(公告)日：2020-01-16

    申请号：US16035024

    申请日：2018-07-13

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Ilker Deligoz

    IPC: H03L7/07 ,  G06F1/10 ,  H03L7/099 ,  H03L7/08

    Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

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