公开(公告)号：US20250072110A1

公开(公告)日：2025-02-27

申请号：US18454376

申请日：2023-08-23

Applicant: QUALCOMM Incorporated

Inventor： Kamesh MEDISETTI ,  Sharad Kumar GUPTA ,  Sudesh Chandra SRIVASTAVA ,  Somesh AGARWAL ,  Udayakiran Kumar YALLAMARAJU ,  Anand Ashok BALIGATTI ,  Girish T P ,  Ankur MEHROTRA ,  Gousulu KANDUKURU ,  Abhinav CHAUHAN ,  Amit KASHYAP ,  Parissa NAJDESAMII

IPC: H01L27/118

Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.