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Patent Agency Ranking
公开(公告)号：US20250045091A1
公开(公告)日：2025-02-06
申请号：US18364037
申请日：2023-08-02
Applicant: QUALCOMM Incorporated
Inventor： Rohan Desai , Abhilash Shivashankara Pillai , Rajakumar Govindaram , Satish Goverdhan , Pavan Kumar Chilamkurthi , Wesley James Holland
Abstract: A multi-core processing system, such as a system-on-chip (SOC), is configured to use interrupts when sending processed data from a source processing core to a destination processing core. The source processing core may delay sending interrupts, but still keep processing data, when an acknowledgment for a previous interrupt is not received from an inter-processor communication controller. When the acknowledgment is received, the source processing core may resume sending an interrupt for the next chunk of data processed. As such, not all chunks of data may have associated interrupts.
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公开(公告)号：US11140375B2
公开(公告)日：2021-10-05
申请号：US16719247
申请日：2019-12-18
Applicant: QUALCOMM Incorporated
Inventor： Wesley James Holland , Satish Goverdhan , Venkata Rajesh Kumar Sastrula , Ramesh Ramaswamy , Songhe Cai , Ling Feng Huang , Chih-Chi Cheng , Huang Huang , Rajakumar Govindaram
IPC: H04N13/139 , H04N13/207 , H04N13/25
Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
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公开(公告)号：US09292293B2
公开(公告)日：2016-03-22
申请号：US14074908
申请日：2013-11-08
Applicant: QUALCOMM Incorporated
Inventor： Hee-Jun Park , Steven S Thomson , Ronald Frank Alton , Edoardo Regini , Satish Goverdhan , Pieter-Louis Dam Backer
CPC classification number: G06F9/38 , G06F1/206 , G06F1/3243 , G06F1/3287 , G06F9/5094 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/22
Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.
Abstract translation: 各方面提供了用于多核集成电路的多个处理器核的智能多核控制的装置和方法。 这些方面可以识别和激活一组最优化的处理器内核，以实现给定工作负载的最低级别功耗或给定功率预算的最高性能。 处理器核心的最佳集合可以是活动处理器核心的数量或特定活动处理器核心的指定。 当处理器核心的温度读数低于阈值时，可以选择一组处理器核以为给定的工作负载提供最低的功耗。 当处理器核心的温度读数高于阈值时，可以选择设置的处理器核心以为给定的功率预算提供最佳性能。
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公开(公告)号：US20190191079A1
公开(公告)日：2019-06-20
申请号：US15849013
申请日：2017-12-20
Applicant: QUALCOMM Incorporated
Inventor： Jignesh Mehta , Mridul Singh , Guruprasad Gaonkar , Pasi Johannes Parkkila , Satish Goverdhan
IPC: H04N5/232
CPC classification number: H04N5/23225 , H04N5/23229 , H04N5/247 , H04N2201/0075
Abstract: Aspects of the present disclosure relate to systems and methods for camera initialization of a multiple camera module. An example device may include one or more processors and a memory including instructions that, when executed by the one or more processors, cause the device to receive a first command for initializing a first camera of a multiple camera module, receive a second command, after receiving the first command, for initializing a second camera of the multiple camera module, receive a third command, after receiving the second command, for initializing the first camera, and execute the first command and the third command before executing the second command.
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公开(公告)号：US20150046685A1
公开(公告)日：2015-02-12
申请号：US14074908
申请日：2013-11-08
Applicant: QUALCOMM Incorporated
Inventor： Hee-Jun Park , Steven S. Thomson , Ronald Frank Alton , Edoardo Regini , Satish Goverdhan , Pieter-Louis Dam Backer
IPC: G06F9/38
CPC classification number: G06F9/38 , G06F1/206 , G06F1/3243 , G06F1/3287 , G06F9/5094 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/22
Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.
Abstract translation: 各方面提供了用于多核集成电路的多个处理器核的智能多核控制的装置和方法。 这些方面可以识别和激活一组最优化的处理器内核，以实现给定工作负载的最低级别功耗或给定功率预算的最高性能。 处理器核心的最佳集合可以是活动处理器核心的数量或特定活动处理器核心的指定。 当处理器核心的温度读数低于阈值时，可以选择一组处理器核以为给定的工作负载提供最低的功耗。 当处理器核心的温度读数高于阈值时，可以选择设置的处理器核心以为给定的功率预算提供最佳性能。
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