公开(公告)号：US20190214076A1

公开(公告)日：2019-07-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish SHANKAR ,  Manish GARG ,  Rahul Krishnakumar NADKARNI ,  Rajesh KUMAR ,  Michael PHAN

IPC: G11C11/419

Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：US20180152176A1

公开(公告)日：2018-05-31

申请号：US15362784

申请日：2016-11-28

Applicant: QUALCOMM Incorporated

Inventor： Shaoping GE ,  Chiaming CHAI ,  Stephen Edward LILES ,  Rahul Krishnakumar NADKARNI

IPC: H03K3/013 ,  H03K3/017

CPC classification number: H03K5/04

Abstract: Systems and methods for pulse generation in a dual voltage domain include a first and a second voltage aware branch sensitive to a low voltage domain. The first voltage aware branch includes an inverter in the low voltage domain for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain. The second voltage aware branch includes a delay element in the low voltage domain for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.

公开(公告)号：US20170288673A1

公开(公告)日：2017-10-05

申请号：US15087812

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Rahul Krishnakumar NADKARNI ,  Anthony CORREALE, JR.

IPC: H03K19/0185 ,  G06F1/32

CPC classification number: H03K19/018521 ,  G06F1/3296 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356147 ,  H03K19/0016 ,  H03K19/01707

Abstract: Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.