-
公开(公告)号:US20240119301A1
公开(公告)日:2024-04-11
申请号:US18464996
申请日:2023-09-11
Applicant: QUALCOMM Incorporated
Inventor: Wonseok JEON , Mukul GAGRANI , Weiliang ZENG , Edward TEAGUE , Burak BARTAN , Piero ZAPPI , Christopher LOTT
IPC: G06N3/092
CPC classification number: G06N3/092
Abstract: A processor-implemented method includes sampling, according to a priority sampling policy, a set of node priorities from a computation graph. Each node priority of the set of node priorities may be associated with a respective node on the computation graph. Additionally, each node may represent an operation of a task performed by an artificial neural network. The method also includes converting, via a list scheduling function, the node priorities to a schedule that associates each node of the computation graph with a processor of a group of processors of a device associated with the artificial neural network, the schedule associated with a makespan. The method further includes performing the task in accordance with the schedule.
-
公开(公告)号:US20250094780A1
公开(公告)日:2025-03-20
申请号:US18468203
申请日:2023-09-15
Applicant: QUALCOMM Incorporated
Inventor: Kartikeya BHARDWAJ , Piero ZAPPI , Paul Nicholas WHATMOUGH , Christopher LOTT , Viswanath GANAPATHY , Chirag Sureshbhai PATEL , Joseph Binamira SORIAGA
IPC: G06N3/0464
Abstract: Certain aspects provide techniques and apparatuses for efficiently processing inputs in a neural network using multiple receptive field sizes. An example method includes partitioning a first input into a first set of channels and a second set of channels. At a first layer of a neural network, the first set of channels and the second set of channels are convolved into a first output having a smaller dimensionality a dimensionality of the first input. The first set of channels and the first output are concatenated into a second input. The second input is convolved into a second output via a second layer of the neural network, wherein the second output merges a first receptive field generated by the first layer with a larger second receptive field generated by the second layer. One or more actions are taken based on at least one of the first output and the second output.
-
公开(公告)号:US20240211312A1
公开(公告)日:2024-06-27
申请号:US18086611
申请日:2022-12-21
Applicant: QUALCOMM Incorporated
Inventor: Weiliang ZENG , Christopher LOTT , Edward TEAGUE , Yang YANG , Wonseok JEON , Muntasir Amin MALLICK , Mukul GAGRANI , Piero ZAPPI , Joseph Binamira SORIAGA
IPC: G06F9/50
CPC classification number: G06F9/5027
Abstract: A processor-implemented method for compiler optimization using node symmetry includes receiving a representation of an artificial neural network (ANN) include multiple nodes coupled via multiple edges. One or more symmetric sets of nodes are determined based on one or more of a set of attributes for each node or a connectivity of the nodes via the edges. One or more of an order or a schedule for executing the nodes is generated based on the one or more symmetric sets of nodes.
-
公开(公告)号:US20240037150A1
公开(公告)日:2024-02-01
申请号:US17878677
申请日:2022-08-01
Applicant: QUALCOMM Incorporated
Inventor: Yang YANG , Mukul GAGRANI , Wonseok JEON , Edward TEAGUE , Weiliang ZENG , Piero ZAPPI , Corrado RAINONE , Christopher LOTT
IPC: G06F16/901 , G06N5/02
CPC classification number: G06F16/9024 , G06N5/022
Abstract: A processor-implemented method for generating a schedule for executing operations of a compute graph includes receiving a graph including multiples nodes connected by edges. Each of the multiple nodes represents an operation to be executed. A set of sequences for executing the nodes is determined based on one or more precedence constraints. One or more sequences are selected from the set of sequences based on a memory constraint associated with a device for executing the nodes. A schedule for executing the nodes on the device is generated based on the selected one or more sequences.
-
公开(公告)号:US20240118923A1
公开(公告)日:2024-04-11
申请号:US18459277
申请日:2023-08-31
Applicant: QUALCOMM Incorporated
Inventor: Corrado RAINONE , Wei David ZHANG , Roberto BONDESAN , Markus PESCHL , Mukul GAGRANI , Wonseok JEON , Edward TEAGUE , Piero ZAPPI , Weiliang ZENG , Christopher LOTT
IPC: G06F9/48
CPC classification number: G06F9/4881 , G06N5/04
Abstract: A processor-implemented method includes generating, by a scheduling model, a group of schedules from a computation graph associated with a task, each node on the computation graph being associated with an operation of an artificial neural network, each schedule of the group of schedules associating each node of the computation graph with a processor of a group of processors of a hardware device. The processor-implemented method also includes testing one or more schedules of the group of schedules on the hardware device or a model of the hardware device. The processor-implemented method further includes selecting a schedule of the one or more schedules based on testing the one or more schedules, the selected schedule satisfying a selection condition.
-
公开(公告)号:US20230376735A1
公开(公告)日:2023-11-23
申请号:US18103757
申请日:2023-01-31
Applicant: QUALCOMM Incorporated
Inventor: Corrado RAINONE , Mukul GAGRANI , Yang YANG , Roberto BONDESAN , Edward TEAGUE , Christopher LOTT , Wonseok JEON , Weiliang ZENG , Piero ZAPPI , Herke VAN HOOF
Abstract: A processor-implemented method for generating a topological order using an artificial neural network (ANN) includes receiving a set of tasks to be performed. The tasks are represented in a graph including multiple nodes connected by edges. Each node corresponds to a task in the set of tasks. A scheduling priority is assigned to each node in the graph. A next node of potential next nodes is selected according to a probability of each of the potential next nodes based on the assigned scheduling priorities and a topology of the graph. A topological order of the tasks is generated by repeating the selection of the next node.
-
公开(公告)号:US20210182684A1
公开(公告)日:2021-06-17
申请号:US17121499
申请日:2020-12-14
Applicant: QUALCOMM Incorporated
Inventor: Piero ZAPPI , Jin Won LEE , Christopher LOTT , Rexford Alan HILL
Abstract: A method performed by a computing device includes determining a partition for depth-first processing by a multi-layer artificial neural network (ANN) of the computing device. The computing device comprising a processor, on-chip memory, and off-chip memory. The first partition determined based on an amount of on-chip memory used by the first partition, an available amount of on-chip memory, and a size of a write back to the off-chip memory. The method also includes processing, at the device via the multi-layer ANN, an input, using the depth-first processing in accordance with the partition.
-
8.
公开(公告)号:US20170059401A1
公开(公告)日:2017-03-02
申请号:US14843790
申请日:2015-09-02
Applicant: QUALCOMM Incorporated
Inventor: Santiago MAZUELAS , Ashwin SWAMINATHAN , Piero ZAPPI , Muralidhar Reddy AKULA , Abhijeet BISAIN , Aditya Narain SRIVASTAVA , Suhas Hariharapura SHESHADRI
CPC classification number: G01J1/44 , G01J1/4204 , G01J2001/444 , G06F9/4405 , H04M1/22 , H04M1/72569 , H04M2250/12
Abstract: A method of auto-calibrating light sensor data of a mobile device includes, obtaining, by the mobile device, one or more reference parameters representative of light sensor data collected by a reference device. The method also includes collecting, by the mobile device, light sensor data from a light sensor included in the mobile device, itself. One or more sample parameters of the light sensor data obtained from the light sensor included in the mobile device are then calculated. A calibration model is then determined for auto-calibrating the light sensor data of the light sensor included in the mobile device based on the one or more reference parameters and the one or more sample parameters.
Abstract translation: 自动校准移动设备的光传感器数据的方法包括:由移动设备获得表示由参考设备收集的光传感器数据的一个或多个参考参数。 该方法还包括由移动设备从包括在移动设备中的光传感器本身收集光传感器数据。 然后计算从包括在移动设备中的光传感器获得的光传感器数据的一个或多个采样参数。 然后,基于一个或多个参考参数和一个或多个样本参数,确定校准模型,用于自动校准包括在移动设备中的光传感器的光传感器数据。
-
-
-
-
-
-
-