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公开(公告)号：US20220077830A1
公开(公告)日：2022-03-10
申请号：US17017239
申请日：2020-09-10
Applicant: QUALCOMM Incorporated
Abstract: A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.
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公开(公告)号：US20210336760A1
公开(公告)日：2021-10-28
申请号：US17305542
申请日：2021-07-09
Applicant: QUALCOMM Incorporated
Inventor： Ying DUAN , Jing WU , Shih-Wei CHOU
IPC: H04L7/00
Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
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公开(公告)号：US20210126765A1
公开(公告)日：2021-04-29
申请号：US17001801
申请日：2020-08-25
Applicant: QUALCOMM Incorporated
Inventor： Ying DUAN , Jing WU , Shih-Wei CHOU
IPC: H04L7/00
Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
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