公开(公告)号：US10084621B2

公开(公告)日：2018-09-25

申请号：US15422050

申请日：2017-02-01

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

IPC: H03D3/18 ,  H03D3/24 ,  H04L25/03 ,  H04L12/26 ,  H04L27/00

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：US10049067B2

公开(公告)日：2018-08-14

申请号：US15367071

申请日：2016-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xiaohua Kong ,  Deqiang Song ,  Zhi Zhu ,  Ohjoon Kwon

IPC: G06F13/38 ,  G06F13/42 ,  G06F3/14

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

公开(公告)号：US20180157609A1

公开(公告)日：2018-06-07

申请号：US15367071

申请日：2016-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xiaohua Kong ,  Deqiang Song ,  Zhi Zhu ,  Ohjoon Kwon

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F3/14 ,  G06F13/4282

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

公开(公告)号：US20180219704A1

公开(公告)日：2018-08-02

申请号：US15422050

申请日：2017-02-01

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

IPC: H04L25/03 ,  H04L12/26

CPC classification number: H04L25/03273 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337 ,  H04L43/16 ,  H04L2027/0069

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：US09729163B1

公开(公告)日：2017-08-08

申请号：US15251861

申请日：2016-08-30

Applicant: QUALCOMM Incorporated

Inventor： Deqiang Song ,  Xiaohua Kong ,  Bupesh Pandita ,  Zhuo Gao

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

CPC classification number: H03M1/06 ,  G01R31/316 ,  G01R31/3167 ,  H03M1/1009 ,  H03M1/12

Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.