公开(公告)号：US11942933B2

公开(公告)日：2024-03-26

申请号：US17521651

申请日：2021-11-08

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Aliasgar Presswala ,  Chiew-Guan (Kelvin) Tan

IPC: H03K19/0185 ,  H03K3/037 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K3/0375 ,  H03K19/00315

Abstract: An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.

公开(公告)号：US10700683B1

公开(公告)日：2020-06-30

申请号：US16114524

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Sumit Rao

IPC: H03K19/00 ,  H03K5/08 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185 ,  G06F1/26 ,  H03K3/3565 ,  H03K17/10

Abstract: Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal into a low-voltage signal. The high voltage input signal is split into a upper portion and a lower portion. The upper portion is coupled to a high input receiver that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

公开(公告)号：US20160248418A1

公开(公告)日：2016-08-25

申请号：US14631347

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K17/26 ,  H03K17/18

CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

公开(公告)号：US11637356B1

公开(公告)日：2023-04-25

申请号：US17649526

申请日：2022-01-31

Applicant: QUALCOMM Incorporated

Inventor： Aliasgar Presswala ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0185 ,  H01P5/12 ,  H02M3/155

Abstract: In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.

公开(公告)号：US09484911B2

公开(公告)日：2016-11-01

申请号：US14631347

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/01 ,  H03K17/26 ,  H03K17/18

CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

公开(公告)号：US09184735B1

公开(公告)日：2015-11-10

申请号：US14254706

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：US20140091860A1

公开(公告)日：2014-04-03

申请号：US13683053

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: G05F1/565

CPC classification number: G05F1/565

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract translation: 公开了一种输入/输出（I / O）驱动器，其采用补偿电路来限制驱动器的器件之间的电压超过限定的阈值，以允许较低电压的器件实现驱动器的操作。 特别地，驱动器采用包括耦合在第一电压轨和驱动器的输出之间的第一和第二开关器件的上拉电路。 驱动器采用包括耦合在输出端和第二电压轨道之间的第三和第四开关器件的下拉电路。 I / O驱动器采用补偿电路，其被配置为在适当的时间向第一和第二开关器件之间的节点和第三和第四开关器件之间的节点施加补偿电压，以保持跨越第二和第三开关器件的相应电压 在驾驶员的操作期间，切换设备处于或低于定义的阈值，例如可靠性限制。

公开(公告)号：US11595042B1

公开(公告)日：2023-02-28

申请号：US17526805

申请日：2021-11-15

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan (Kelvin) Tan

IPC: H03K3/00 ,  H03K17/10 ,  H03K17/66 ,  H03K17/687 ,  H04B1/40

Abstract: An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

公开(公告)号：US11251794B2

公开(公告)日：2022-02-15

申请号：US17008068

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Sumit Rao ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/003

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

公开(公告)号：US11171649B1

公开(公告)日：2021-11-09

申请号：US17071796

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Aliasgar Presswala ,  Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K3/356

Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.