公开(公告)号：US20220129200A1

公开(公告)日：2022-04-28

申请号：US17445220

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Victor VAN DER VEEN ,  Mosaddiq SAIFUDDIN ,  Pankaj DESHMUKH ,  Behnam DASHTIPOUR ,  David HARTLEY

IPC: G06F3/06

Abstract: A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.

公开(公告)号：US20240087639A1

公开(公告)日：2024-03-14

申请号：US17940430

申请日：2022-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： Victor VAN DER VEEN ,  Pankaj DESHMUKH ,  Behnam DASHTIPOUR ,  David HARTLEY

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40611 ,  G11C11/40618

Abstract: Mitigating or managing an effect known as “rowhammer” upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directed to the DRAM device and count the number of the row activation commands. The memory controller may send a mitigative refresh command to the DRAM device based on the result of comparing the counted number of row activation commands with the received activation count threshold value.

公开(公告)号：US20240312508A1

公开(公告)日：2024-09-19

申请号：US18184602

申请日：2023-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Victor VAN DER VEEN ,  David HARTLEY

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4078

Abstract: Managing row hammering in a DRAM device may include maintaining per-row activation command counts. A next aggressor row may be determined based on the counts. A victim queue may be maintained. A refresh operation may be directed to a row indicated by the victim queue when conditions include that the victim queue is not empty when the refresh command is received. The current aggressor row may be updated with the next aggressor row when conditions include that the victim queue is empty when the refresh command is received. Following updating the current aggressor row, the count of the next aggressor row may be updated. A victim row corresponding to the current aggressor row may be added to the victim queue if the victim queue is empty when the refresh command is received.

公开(公告)号：US20230410882A1

公开(公告)日：2023-12-21

申请号：US17842606

申请日：2022-06-16

Applicant: QUALCOMM Incorporated

Inventor： Akash VERMA ,  Victor VAN DER VEEN ,  Joona Verneri KANNISTO ,  Marcel SELHORST

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/4087 ,  G11C11/40615 ,  G11C11/40618

Abstract: The present disclosure generally relates to techniques for defending against row hammer attacks. Some aspects of the present disclosure include systems and techniques for defending against row hammer attacks using dynamic assignment of guard rows. One example computing device for memory protection generally includes at least one memory and one or more processors coupled to the at least one memory and configured to: receive a first memory assignment for a service; determine, in response to receiving the first memory assignment, that the service is associated with a type of data; assign guard rows adjacent to a memory subset to protect the memory subset based on the determination; and dedicate at least a portion of the memory subset for storage of data for the service.