公开(公告)号：US20230410882A1

公开(公告)日：2023-12-21

申请号：US17842606

申请日：2022-06-16

Applicant: QUALCOMM Incorporated

Inventor： Akash VERMA ,  Victor VAN DER VEEN ,  Joona Verneri KANNISTO ,  Marcel SELHORST

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/4087 ,  G11C11/40615 ,  G11C11/40618

Abstract: The present disclosure generally relates to techniques for defending against row hammer attacks. Some aspects of the present disclosure include systems and techniques for defending against row hammer attacks using dynamic assignment of guard rows. One example computing device for memory protection generally includes at least one memory and one or more processors coupled to the at least one memory and configured to: receive a first memory assignment for a service; determine, in response to receiving the first memory assignment, that the service is associated with a type of data; assign guard rows adjacent to a memory subset to protect the memory subset based on the determination; and dedicate at least a portion of the memory subset for storage of data for the service.

公开(公告)号：US20240370575A1

公开(公告)日：2024-11-07

申请号：US18691811

申请日：2022-08-03

Applicant: QUALCOMM Incorporated

Inventor： Marcel SELHORST ,  Alexander DENT ,  Joona Verneri KANNISTO ,  Akash VERMA

IPC: G06F21/57

Abstract: Various embodiments include methods and devices for circumventing processor error induced vulnerability. Embodiments may include determining whether a condition indicative of an error in a processor exists for a first processor, and preventing use of the first processor in response to determining that the condition indicative of the error in the processor exists for the first processor. In some embodiments, preventing use of the first processor may include transitioning the first processor to a low power state. In some embodiments, preventing use of the first processor may include preventing the first processor from being registered with an operating system. In some embodiments, the condition indicative of the error in the processor may include an enabled non-secure debug feature of the processor and a disabled secure debug feature of the processor.