公开(公告)号：US20250103545A1

公开(公告)日：2025-03-27

申请号：US18473119

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR

IPC: G06F15/78

Abstract: A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

公开(公告)号：US20230401156A1

公开(公告)日：2023-12-14

申请号：US17806291

申请日：2022-06-10

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/123

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/124

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

公开(公告)号：US20250117346A1

公开(公告)日：2025-04-10

申请号：US18482793

申请日：2023-10-06

Applicant: QUALCOMM Incorporated

Inventor： Mohd SALMAN ,  Utkarsh VINAYAK ,  Sharath Kumar NAGILLA ,  Hithesh Hassan LEPAKSHA

IPC: G06F13/26

Abstract: Aspects of the disclosure are directed to interrupt handling. In accordance with one aspect, disclosed includes a first processing engine; a second processing engine; and a timeout monitoring block coupled to the first processing engine and the second processing engine, wherein the timeout monitoring block is configured to reaffinitize an interrupt affined to the first processing engine to the second processing engine. Also disclosed for interrupt handling includes placing a first interrupt into a pending state; initiating a handling of a second interrupt; initiating a programmed timeout value; triggering a timeout state of the first interrupt when an interrupt timer reaches the programmed timeout value; and entering a reaffinitization state of the first interrupt after the timeout state is triggered.

公开(公告)号：US20250036574A1

公开(公告)日：2025-01-30

申请号：US18359407

申请日：2023-07-26

Applicant: QUALCOMM Incorporated

Inventor： Chandrashekar Reddy KUNREDDY ,  Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA

IPC: G06F12/14 ,  G06F12/1009 ,  G06F21/44 ,  G06F21/62

Abstract: Aspects relate to rejecting a cache access packet using a mapping table. A cache has slices. An interconnect controller is coupled to the cache and coupled to a plurality of masters and configured to receive a cache access packet from a master. The cache access packet includes a first master identifier to identify the master, a first sub-cache index identifier to identify a slice of the cache, and an operation to be performed on the cache. A mapping table has master identifiers associated with sub-cache index identifiers and compare logic compares the first master identifier and the first sub-cache index identifier to the mapping table. The interconnect controller rejects the cache access packet in response to the first master identifier not being associated with the first sub-cache index identifier in the mapping table.

公开(公告)号：US20230401152A1

公开(公告)日：2023-12-14

申请号：US17827302

申请日：2022-05-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/468

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

公开(公告)号：US20250103522A1

公开(公告)日：2025-03-27

申请号：US18473948

申请日：2023-09-25

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Kalangi Fredy SUNDAR ,  Raveesh SINHA

IPC: G06F13/16 ,  G06F11/30 ,  G06F13/42

Abstract: Aspects relate to using memory access latency to mitigate thermal excesses in a System on a Chip (SOC). An apparatus includes a processing core, a memory, and thermal monitor configured to determine a thermal state of the processing core. A memory controller is coupled to the processing core, to the thermal monitor, and to the memory, and configured to provide the processing core with access to the memory, the memory controller further configured to delay access to the memory in response to the thermal state.

公开(公告)号：US20240361931A1

公开(公告)日：2024-10-31

申请号：US18307686

申请日：2023-04-26

Applicant: QUALCOMM INCORPORATED

Inventor： Hithesh Hassan LEPAKSHA ,  Darshan Kumar NANDANWAR ,  Sharath Kumar NAGILLA

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0685

Abstract: Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.