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    OPTIMIZED MULTI-PASS RENDERING ON TILED BASE ARCHITECTURES
    1.
    发明申请
    OPTIMIZED MULTI-PASS RENDERING ON TILED BASE ARCHITECTURES 有权

    公开(公告)号：US20160148338A1

    公开(公告)日：2016-05-26

    申请号：US15012467

    申请日：2016-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T1/20

    CPC classification number: G06T1/20 ,  G06T15/005

    Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.

    Conditional execution of rendering commands based on per bin visibility information with added inline operations
    2.
    发明授权
    Conditional execution of rendering commands based on per bin visibility information with added inline operations 有权
    有条件地执行渲染命令基于每个bin可见性信息添加内联操作

    公开(公告)号：US09286649B2

    公开(公告)日：2016-03-15

    申请号：US14059076

    申请日：2013-10-21

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T15/40 ,  G06T1/20 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T15/005

    Abstract: A GPU may determine, based on a visibility stream, whether to execute instructions stored in an indirect buffer. The instructions include instructions for rendering primitives associated with a bin of a plurality of bins and include one or more secondary operations. The visibility stream indicate if one or more of the primitives associated with the bin will be visible in a finally rendered scene. The GPU may, responsive to determining not to execute the instructions stored in the indirect buffer, execute one or more secondary operations stored in a shadow indirect buffer. The GPU may, responsive to determining to execute the instructions stored in the indirect buffer, execute the instructions for rending the primitives associated with the bin of the plurality of bins and executing the one or more secondary operations stored in the indirect buffer.

    Abstract translation: GPU可以基于可见性流来确定是否执行存储在间接缓冲器中的指令。 所述指令包括用于呈现与多个箱体的仓相关联的基元的指令，并且包括一个或多个次要操作。 可见性流指示与最后呈现的场景中是否可以看到与该仓相关联的一个或多个图元。 GPU可以响应于确定不执行存储在间接缓冲器中的指令，执行存储在阴影间接缓冲器中的一个或多个次要操作。 GPU可以响应于确定执行存储在间接缓冲器中的指令，执行用于重现与多个箱体的仓相关联的图元的指令，并执行存储在间接缓冲器中的一个或多个二次操作。

    Graphics memory load mask for graphics processing
    3.
    发明授权
    Graphics memory load mask for graphics processing 有权
    用于图形处理的图形存储器加载掩码

    公开(公告)号：US09280956B2

    公开(公告)日：2016-03-08

    申请号：US13688748

    申请日：2012-11-29

    Applicant: QUALCOMM Incorporated

    Inventor： Avinash Seetharamaiah ,  Christopher Paul Frascati

    IPC: G09G5/393 ,  G09G5/00 ,  G06T1/60 ,  G06T15/00

    CPC classification number: G09G5/393 ,  G06T1/60 ,  G06T15/005 ,  G09G5/001

    Abstract: Systems and methods are described including creating a mask that indicates which pixel groups do not need to be loaded from Graphics Memory (GMEM). The mask indicates a pixel group does not need to be loaded from GMEM. The systems and methods may further include rendering a tile on a screen. This may include loading the GMEM based on the indication from the mask and skipping a load from the GMEM based on the indication from the mask.

    Abstract translation: 描述了系统和方法，包括创建指示不需要从图形存储器（GMEM）加载哪些像素组的掩码。 掩码表示不需要从GMEM加载像素组。 系统和方法还可以包括在屏幕上渲染瓦片。 这可以包括基于掩码的指示加载GMEM，并基于掩码的指示从GMEM跳过负载。

    CONDITIONAL EXECUTION OF RENDERING COMMANDS BASED ON PER BIN VISIBILITY INFORMATION WITH ADDED INLINE OPERATIONS
    4.
    发明申请
    CONDITIONAL EXECUTION OF RENDERING COMMANDS BASED ON PER BIN VISIBILITY INFORMATION WITH ADDED INLINE OPERATIONS 有权
    基于增加的在线操作的每个可见性信息的渲染命令的条件执行

    公开(公告)号：US20140354661A1

    公开(公告)日：2014-12-04

    申请号：US14059076

    申请日：2013-10-21

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T1/20

    CPC classification number: G06T1/20 ,  G06T15/005

    Abstract: A GPU may determine, based on a visibility stream, whether to execute instructions stored in an indirect buffer. The instructions include instructions for rendering primitives associated with a bin of a plurality of bins and include one or more secondary operations. The visibility stream indicate if one or more of the primitives associated with the bin will be visible in a finally rendered scene. The GPU may, responsive to determining not to execute the instructions stored in the indirect buffer, execute one or more secondary operations stored in a shadow indirect buffer. The GPU may, responsive to determining to execute the instructions stored in the indirect buffer, execute the instructions for rending the primitives associated with the bin of the plurality of bins and executing the one or more secondary operations stored in the indirect buffer.

    Abstract translation: GPU可以基于可见性流来确定是否执行存储在间接缓冲器中的指令。 所述指令包括用于呈现与多个箱体的仓相关联的基元的指令，并且包括一个或多个次要操作。 可见性流指示与最后呈现的场景中是否可以看到与该仓相关联的一个或多个图元。 GPU可以响应于确定不执行存储在间接缓冲器中的指令，执行存储在阴影间接缓冲器中的一个或多个次要操作。 GPU可以响应于确定执行存储在间接缓冲器中的指令，执行用于重现与多个箱体的仓相关联的图元的指令，并执行存储在间接缓冲器中的一个或多个二次操作。

    Command instruction management
    8.
    发明授权
    Command instruction management 有权
    命令指令管理

    公开(公告)号：US09165337B2

    公开(公告)日：2015-10-20

    申请号：US14027816

    申请日：2013-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06F13/28 ,  G06T1/20 ,  G06F9/38 ,  G06F9/50 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06F9/3881 ,  G06F9/50 ,  G06F9/5022 ,  G06T1/60

    Abstract: Techniques are described for writing commands to memory units of a chain of memory units of a command buffer. The techniques may write the commands, and if during the writing, it is determined that there is not sufficient space in the chain of memory unit, the techniques may flush previously confirmed commands. If after the writing, the techniques determine that there is not sufficient space in an allocation list for the handles associated with the commands, the techniques may flush previously confirmed commands.

    Abstract translation: 描述了将命令写入命令​​缓冲器的存储器单元链的存储器单元的技术。 这些技术可以写入命令，并且如果在写入期间确定存储器单元链中没有足够的空间，则这些技术可以刷新先前确认的命令。 如果在写入之后，这些技术确定在与命令相关联的句柄的分配列表中没有足够的空间，该技术可以冲洗以前确认的命令。

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