公开(公告)号：US20160203083A1

公开(公告)日：2016-07-14

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  KRISHNA VSSSR VANKA ,  SRAVAN KUMAR AMBAPURAM ,  SHIRISH KUMAR AGARWAL ,  ASHVINKUMAR NAMJOSHI ,  HARSHAD BHUTADA

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract translation: 描述了多集群异构处理器架构中的动态缓存扩展。 一个实施例是包括具有第一级二（L2）高速缓存的第一处理器集群和具有第二L2高速缓存的第二处理器集群的系统。 该系统还包括与第一和第二L2高速缓存通信的控制器。 控制器从第一处理器集群接收处理器工作负载输入和高速缓存工作负载输入。 基于处理器工作负载输入和缓存工作负荷输入，高速缓存控制器确定与第一处理器集群相关联的当前任务是否受到第一L2高速缓存的大小阈值或第一处理器集群的性能阈值的限制。 如果当前任务受到第一L2高速缓存的大小阈值的限制，则控制器使用第二L2高速缓存的至少一部分作为第一L2高速缓存的扩展。