公开(公告)号：US11430538B1

公开(公告)日：2022-08-30

申请号：US17195547

申请日：2021-03-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Pochiao Chou ,  Cheng-Che Yang

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.

公开(公告)号：US20220254431A1

公开(公告)日：2022-08-11

申请号：US17195547

申请日：2021-03-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Pochiao Chou ,  Cheng-Che Yang

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.