公开(公告)号：US12088937B2

公开(公告)日：2024-09-10

申请号：US17658559

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Rui Wang ,  Lihang Fan

IPC: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

CPC classification number: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

公开(公告)号：US11683602B1

公开(公告)日：2023-06-20

申请号：US17716856

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Lihang Fan

IPC: H04N25/615 ,  H04N25/133 ,  H04N25/13 ,  H04N25/447

CPC classification number: H04N25/6153 ,  H04N25/133 ,  H04N25/134 ,  H04N25/447

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

公开(公告)号：US11871135B2

公开(公告)日：2024-01-09

申请号：US17592389

申请日：2022-02-03

Applicant: OmniVision Technologies, Inc.

Inventor： Selcuk Sen ,  Liang Zuo ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Hiroaki Ebihara

IPC: H04N25/779 ,  H01L27/146 ,  H04N25/621 ,  H04N25/76 ,  H04N25/60 ,  H04N25/704 ,  H04N25/42 ,  H04N25/13

CPC classification number: H04N25/779 ,  H01L27/14609 ,  H01L27/14643 ,  H04N25/42 ,  H04N25/60 ,  H04N25/623 ,  H04N25/704 ,  H04N25/76 ,  H04N25/134

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

公开(公告)号：US20230328405A1

公开(公告)日：2023-10-12

申请号：US17658559

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Rui Wang ,  Lihang Fan

IPC: H04N5/369 ,  H04N5/378

CPC classification number: H04N5/3698 ,  H04N5/36961 ,  H04N5/378

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

公开(公告)号：US11683604B1

公开(公告)日：2023-06-20

申请号：US17678533

申请日：2022-02-23

Applicant: OmniVision Technologies, Inc.

Inventor： Liang Zuo ,  Rui Wang ,  Selcuk Sen ,  Xuelian Liu ,  Min Qu ,  Hiroaki Ebihara

IPC: H04N25/704 ,  H04N25/11 ,  H04N25/60

CPC classification number: H04N25/704 ,  H04N25/11 ,  H04N25/60

Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.