公开(公告)号：US20130320400A1

公开(公告)日：2013-12-05

申请号：US13895228

申请日：2013-05-15

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria HURKX ,  Jeroen Antoon CROON ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John SQUE ,  Andreas Bernardus Maria JANSMAN ,  Markus MUELLER ,  Stephan HEIL ,  Tim BOETTCHER

IPC: H01L29/47 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20220284099A1

公开(公告)日：2022-09-08

申请号：US17189329

申请日：2021-03-02

Applicant: NXP B.V.

Inventor： Andreas Bernardus Maria JANSMAN ,  Andreas Lentz

IPC: G06F21/56 ,  H03K3/03 ,  H03K21/02 ,  H03K3/037 ,  G06F1/28 ,  G06F1/3296 ,  G06F21/81

Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.