公开(公告)号：US20170063358A1

公开(公告)日：2017-03-02

申请号：US15243237

申请日：2016-08-22

Applicant: MediaTek Inc.

Inventor： Yi-Feng CHEN ,  Ya-Shih HUANG ,  Chun-Sheng HUANG ,  Yiwei CHEN

IPC: H03K5/15

CPC classification number: H03K5/15 ,  H03K5/135 ,  H03K2005/00019

Abstract: A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

Abstract translation: 提供时钟缓冲电路。 时钟缓冲电路接收输入时钟信号并产生延迟时钟信号。 时钟缓冲电路包括输入电路，输出电路，第一延迟路径和第二延迟路径。 输入电路接收输入时钟信号，并根据输入时钟信号产生输出时钟信号。 输出电路产生延迟时钟信号。 第一延迟路径耦合在输入电路和输出电路之间。 第二延迟路径耦合在输入电路和输出电路之间。 输入电路根据控制信号选择性地将输出时钟信号提供给第一和第二延迟路径中的第一特定延迟路径。 输出电路接收通过第一特定延迟路径的输出时钟信号并输出​​延迟时钟信号。

公开(公告)号：US20160156360A1

公开(公告)日：2016-06-02

申请号：US14881505

申请日：2015-10-13

Applicant: MediaTek Inc.

Inventor： Yi-Feng CHEN ,  Tsung-Ying TSAI ,  Heng-Meng LIU ,  Sung-Yun HSUEH

IPC: H03L7/00 ,  H03K3/03

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03L7/00

Abstract: A signal generator includes a main ring oscillator and a first ring oscillator. The main ring oscillator is supplied by a power voltage, and is configured to generate an output oscillation signal. The main ring oscillator is coupled through a power mesh to the power voltage. The first ring oscillator is supplied by the power voltage. The first ring oscillator is similar or identical to the main ring oscillator. The first ring oscillator is coupled through the power mesh to the power voltage. The first ring oscillator is used to calibrate a frequency of the output oscillation signal.

Abstract translation: 信号发生器包括主环形振荡器和第一环形振荡器。 主环形振荡器由电源电压提供，并被配置为产生输出振荡信号。 主环形振荡器通过功率网连接到电源电压。 第一个环形振荡器由电源电压供电。 第一个环形振荡器与主环形振荡器相似或相同。 第一个环形振荡器通过功率网耦合到电源电压。 第一个环形振荡器用于校准输出振荡信号的频率。

公开(公告)号：US20160153840A1

公开(公告)日：2016-06-02

申请号：US14855592

申请日：2015-09-16

Applicant: MediaTek Inc.

Inventor： Bo-Jr HUANG ,  Yi-Feng CHEN ,  Jia-Wei FANG

IPC: G01K7/00 ,  H03K3/011 ,  H02M7/537 ,  H03K3/03

CPC classification number: G01K7/01 ,  G01K7/00 ,  H03K3/0315

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Abstract translation: 本发明提供一种逆变器。 逆变器包括第一转换器和第二转换器。 第一转换器耦合在逆变器的电源电压和输出节点之间。 第二转换器耦合在逆变器的输出节点和接地电压之间。 第一转换器，第二转换器或二者都包括二极管连接的晶体管。 逆变器的传播延迟时间基本上是逆变器温度的线性函数。

公开(公告)号：US20160197071A1

公开(公告)日：2016-07-07

申请号：US14861461

申请日：2015-09-22

Applicant: MediaTek Inc.

Inventor： Chao-Yang YEH ,  Yi-Feng CHEN ,  Jia-Wei FANG ,  Yao-Tsung HUANG ,  Ming-Cheng LEE

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/283

CPC classification number: H01L27/0805 ,  H01L23/485 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/86

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate. An isolation structure is positioned in the semiconductor substrate. A first electrode and a second electrode are positioned on the semiconductor substrate and coupled to different voltage supplies. The first electrode laterally or parallelly overlaps the second electrode. The first electrode and the second electrode vertically overlap the isolation structure. As a result, leakage current is mitigated or eliminated so that the reliability and performance of the integrated circuit device are improved.

Abstract translation: 本发明提供一种集成电路装置。 集成电路器件包括半导体衬底。 隔离结构位于半导体衬底中。 第一电极和第二电极位于半导体衬底上并耦合到不同的电压源。 第一电极横向或平行地与第二电极重叠。 第一电极和第二电极垂直重叠隔离结构。 结果，泄漏电流被减轻或消除，从而提高了集成电路器件的可靠性和性能。