公开(公告)号：US10514504B2

公开(公告)日：2019-12-24

申请号：US15902455

申请日：2018-02-22

Applicant: Massachusetts Institute of Technology

Inventor： Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

IPC: G02B6/12 ,  G02B6/136 ,  G02B6/132 ,  G02B6/122 ,  G02F1/01 ,  G02F1/025 ,  G02B6/30 ,  G02F1/015

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

公开(公告)号：US20180180811A1

公开(公告)日：2018-06-28

申请号：US15902455

申请日：2018-02-22

Applicant: Massachusetts Institute of Technology

Inventor： Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

IPC: G02B6/136 ,  G02B6/132 ,  G02F1/025 ,  G02B6/122 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/305 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12123 ,  G02F1/0147 ,  G02F1/025 ,  G02F2001/0151

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

公开(公告)号：US10768368B2

公开(公告)日：2020-09-08

申请号：US16680630

申请日：2019-11-12

Applicant: Massachusetts Institute of Technology

Inventor： Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

IPC: G02B6/13 ,  G02B6/136 ,  G02B6/12 ,  G02B6/132 ,  G02B6/122 ,  G02F1/01 ,  G02F1/025 ,  G02B6/30 ,  G02F1/015

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.