公开(公告)号：US20170194984A1

公开(公告)日：2017-07-06

申请号：US15461502

申请日：2017-03-17

Applicant: MEDIATEK INC.

Inventor： Sheng-Jui Huang ,  Michael A. Ashburn, JR. ,  Divya Kesharwani ,  Nathan Egan

IPC: H03M3/00

CPC classification number: H03M3/37 ,  H03M1/86 ,  H03M3/422 ,  H03M3/424 ,  H03M3/428 ,  H03M3/464

Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

公开(公告)号：US20160365870A1

公开(公告)日：2016-12-15

申请号：US15069951

申请日：2016-03-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Jui Huang ,  Michael A. Ashburn, JR. ,  Divya Kesharwani ,  Nathan Egan

IPC: H03M3/00

CPC classification number: H03M3/37 ,  H03M1/86 ,  H03M3/422 ,  H03M3/424 ,  H03M3/428 ,  H03M3/464

Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

Abstract translation: 连续时间Σ-Δ调制器包括基于VCO的量化器，旋转器，截断电路和数模转换器（DAC）。 基于VCO的量化器被布置成基于输入信号和反馈信号生成温度计代码。 旋转器耦合到基于VCO的量化器，并且被布置成基于温度计代码和相移生成相移温度计代码，并且基于相移温度计代码生成重新排列的温度计代码以符合 具体模式。 截断电路耦合到旋转器，并且被布置成从重新排列的温度计代码中提取最高有效位（MSB）部分。 DAC耦合到截断电路，并且被布置成根据至少MSB部分产生反馈信号。 还公开了两种替代的连续时间Σ-Δ调制器。

公开(公告)号：US20180212618A1

公开(公告)日：2018-07-26

申请号：US15875931

申请日：2018-01-19

Applicant: MediaTek Inc.

Inventor： Tao He ,  Michael A. Ashburn, JR.

IPC: H03M3/00

CPC classification number: H03M3/37 ,  H03M3/422 ,  H03M3/464 ,  H03M3/466

Abstract: Circuits for compensating delta-sigma modulators for excess loop delay are described. These circuits may be coupled to quantizers, and may configured to select the threshold values supplied to the quantizers for comparison with an analog signal. The threshold values may each be selected from a corresponding plurality of reference values, and may be set such that the numerical order of threshold values varies over time. For example, the threshold value provided to a first comparator of the quantizer may be greater than the threshold value provided to a second comparator of the quantizer in a first time interval, but the opposite scenario may occur in a second time interval. The circuits may include multiplexers for selecting the threshold values, thermometric encoders, reference selectors and reference multiplexers.

公开(公告)号：US20180212617A1

公开(公告)日：2018-07-26

申请号：US15809476

申请日：2017-11-10

Applicant: MediaTek Inc.

Inventor： Tao He ,  Michael A. Ashburn, JR.

IPC: H03M3/00

CPC classification number: H03M3/322 ,  H03M3/368 ,  H03M3/424 ,  H03M3/464

Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

公开(公告)号：US20180097487A1

公开(公告)日：2018-04-05

申请号：US15465667

申请日：2017-03-22

Applicant: MediaTek Inc.

Inventor： Ayman Shabra ,  Michael A. Ashburn, JR.

IPC: H03F3/45

Abstract: A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.