公开(公告)号：US20150001675A1

公开(公告)日：2015-01-01

申请号：US14490690

申请日：2014-09-19

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/94

Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

Abstract translation: 半导体电路包括第一和第二逻辑电路，第一和第二去耦电容器。 第一去耦电容器布置在第一逻辑电路周围的第一区域中，并且第二去耦电容器布置在第二逻辑电路周围的第二区域中。 其中，第一区域大于第二区域，第一去耦电容器的栅极氧化物厚度大于第二去耦电容器的栅极氧化物厚度，并且第一区域和第一逻辑电路之间的距离短于第 第二区域与第二逻辑电路之间的距离。 此外，第一和第二去耦电容器被设计成没有沟槽。

公开(公告)号：US20140175608A1

公开(公告)日：2014-06-26

申请号：US14190058

申请日：2014-02-25

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811

Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.

Abstract translation: 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同，并且第一区域和第一逻辑电路之间的距离小于第二区域和第二逻辑电路之间的距离。

公开(公告)号：US11728320B2

公开(公告)日：2023-08-15

申请号：US17726595

申请日：2022-04-22

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu Lu ,  Chu-Wei Hu ,  Hsin-Hsin Hsiao

IPC: H01L25/16 ,  H01L23/538

CPC classification number: H01L25/162 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

公开(公告)号：US11342316B2

公开(公告)日：2022-05-24

申请号：US17005528

申请日：2020-08-28

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu Lu ,  Chu-Wei Hu ,  Hsin-Hsin Hsiao

IPC: H05K7/00 ,  H01L25/16 ,  H01L23/538

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.