-
公开(公告)号：US12205624B2
公开(公告)日：2025-01-21
申请号：US18087844
申请日：2022-12-23
Inventor： Hoi Jun Yoo , Wenao Xie
IPC: G11C11/16
Abstract: An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.
-
2.发明公开公开(公告)号：US20230410864A1
公开(公告)日：2023-12-21
申请号：US18087844
申请日：2022-12-23
Inventor： Hoi Jun YOO , Wenao Xie
IPC: G11C11/16
CPC classification number: G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1655
Abstract: An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.
-
Search Results
2
records
(took 0.016 seconds)
