公开(公告)号：US09419736B2

公开(公告)日：2016-08-16

申请号：US13835530

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

IPC: H04J3/04 ,  H03K19/173 ,  H04L25/02

CPC classification number: H04J3/04 ,  H03K19/1737 ,  H04L25/0286

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract translation: 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及被配置为通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

公开(公告)号：US09166605B2

公开(公告)日：2015-10-20

申请号：US13846688

申请日：2013-03-18

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Joon Yeong Lee

IPC: H03L7/00 ,  H03L7/081 ,  H04J3/06 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/081 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0998 ,  H04J3/06

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract translation: 所提出的发明是关于串行和串行收发器应用的改进方法。 所提出的系统包括具有PLL和基于相位旋转器（PR）的延迟锁定环（DLL）的双环路锁相环（PLL）架构。 该架构的优点是单个PLL提供去耦带宽; 用于接收数据的宽抖动容限（JTOL）带宽和用于数据传输的窄抖动传输（JTRAN）带宽。 因此，在提供足够的抖动跟踪带宽的同时，输出端的抖动量可以相对于输入显着减小。 此外，该架构适用于低功耗应用，因为数据路径中的移相器是传统DPLL设计中功耗最大的块之一。

公开(公告)号：US20140269783A1

公开(公告)日：2014-09-18

申请号：US13846688

申请日：2013-03-18

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min BAE ,  Tae Hun Yoon ,  Joon Yeong Lee

IPC: H03L7/081 ,  H04J3/06

CPC classification number: H03L7/081 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0998 ,  H04J3/06

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract translation: 所提出的发明是关于串行和串行收发器应用的改进方法。 所提出的系统包括具有PLL和基于相位旋转器（PR）的延迟锁定环（DLL）的双环路锁相环（PLL）架构。 该架构的优点是单个PLL提供去耦带宽; 用于接收数据的宽抖动容限（JTOL）带宽和用于数据传输的窄抖动传输（JTRAN）带宽。 因此，在提供足够的抖动跟踪带宽的同时，输出端的抖动量可以相对于输入显着减小。 此外，该架构适用于低功耗应用，因为数据通路中的移相器是传统DPLL设计中功耗最大的块之一。

公开(公告)号：US20140269761A1

公开(公告)日：2014-09-18

申请号：US13835530

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

IPC: H04J3/04

CPC classification number: H04J3/04 ,  H03K19/1737 ,  H04L25/0286

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract translation: 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及配置成通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

公开(公告)号：US20140266318A1

公开(公告)日：2014-09-18

申请号：US13843054

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jong Hyeok Yoon

IPC: H03B21/00

CPC classification number: H03B21/00 ,  H03K5/1536 ,  H03M9/00 ,  H04L7/0332

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract translation: 本发明的示例性实施例涉及一种使用相位内插器的输出波形合成器和用于低功率发射器的片上开眼监测（EOM）电路。 为了在发射机设计中实现小面积和低功耗，采用了以子速率工作的单级多相多路复用器。 多相多路复用器由并联开漏NAND门组成。 在子速率发射机架构中，多相时钟信号之间的相位不匹配会显着降低抖动性能，并且是低功耗的广泛使用的关键瓶颈。 为了克服这种不匹配问题，开发了基于面积和功率的相位插值器的波形合成方案。