公开(公告)号：US5546341A

公开(公告)日：1996-08-13

申请号：US441477

申请日：1995-05-15

申请人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

发明人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

CPC分类号： G11C16/16 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage. Channel regions and source and drain junctions of cell units associated with memory transistors programmed to the other binary data are discharged to be programmed while those of cell units associated with nonprogrammed memory transistors are maintained to the program inhibition voltage to prevent programming.

公开(公告)号：US5473563A

公开(公告)日：1995-12-05

申请号：US171300

申请日：1993-12-22

申请人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

发明人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C16/16 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage. Channel regions and source and drain junctions of cell units associated with memory transistors programmed to the other binary data are discharged to be programmed while those of cell units associated with nonprogrammed memory transistors are maintained to the program inhibition voltage to prevent programming.

摘要翻译： 一种包括单元单元阵列的非易失性半导体存储器件，每个单元单元包括具有浮置栅极和控制栅极的至少一个存储晶体管，所述阵列被分成多个存储块，每个存储块具有一定数量的单元单元。 通过施加到半导体衬底的擦除电压擦除所选择的存储块，同时通过擦除电压与连接到未选择存储块的存储晶体管的控制栅极的浮置字线的电容耦合来防止未选择的存储块擦除。 在编程电压被施加到所选择的存储块的所选字线的编程模式中，并且通过电压被施加到所选择的存储块的未选字线，沟道区和源单元的存储晶体管的源极和漏极结 所选存储块被充电到编程禁止电压。 与编程到其他二进制数据的存储器晶体管相关联的单元单元的通道区域和源极和漏极结被放电以进行编程，而与非程序存储晶体管相关联的单元单元的通道区域和漏极结保持在程序禁止电压以防止编程。

公开(公告)号：US5541879A

公开(公告)日：1996-07-30

申请号：US441476

申请日：1995-05-15

申请人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

发明人： Kang D. Suh ,  Jin K. Kim ,  Jeong H. Choi

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/16 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device according to the present invention includes an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. The nonvolatile semiconductor memory device operates in a program mode, a program verify mode and a read mode. A current source provides a predetermined electrical current to the bit lines during both data reading and programming modes, and a common data latch stores program data during a write operation, as well as senses and stores data when the nonvolatile memory device is operated in a data read mode and a program verify mode.

摘要翻译： 根据本发明的非易失性半导体存储器件包括单元单元阵列，每个单元单元包括具有浮置栅极和控制栅极的至少一个存储晶体管，该阵列被分成多个存储块，每个存储块具有一定的 单元数量。 非易失性半导体存储器件在程序模式，程序验证模式和读取模式下操作。 电流源在数据读取和编程模式期间向位线提供预定的电流，并且公共数据锁存器在写入操作期间存储程序数据，并且当非易失性存储器件在数据中被操作时感测和存储数据 读取模式和程序验证模式。