公开(公告)号：US20210303357A1

公开(公告)日：2021-09-30

申请号：US16833595

申请日：2020-03-28

申请人： Intel Corporation

发明人： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

摘要： An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US20240248862A1

公开(公告)日：2024-07-25

申请号：US18424010

申请日：2024-01-26

申请人： INTEL CORPORATION

发明人： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC分类号： G06F13/24 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401

CPC分类号： G06F13/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

摘要： Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20220214737A1

公开(公告)日：2022-07-07

申请号：US17705445

申请日：2022-03-28

申请人： Intel Corporation

发明人： Hisham ABU SALAH ,  Efraim ROTEM ,  Eliezer WEISSMANN ,  Yoni AIZIK ,  Daniel D. LEDERMAN

IPC分类号： G06F1/324 ,  G06F1/3296 ,  G06F1/3206

摘要： In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US20240248722A1

公开(公告)日：2024-07-25

申请号：US18626629

申请日：2024-04-04

申请人： Intel Corporation

发明人： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

摘要： Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20240134443A1

公开(公告)日：2024-04-25

申请号：US18491689

申请日：2023-10-19

申请人： Intel Corporation

发明人： Efraim ROTEM ,  Eliezer WEISSMANN ,  Doron RAJWAN ,  Yoni AIZIK ,  Esfir NATANZON ,  Nir ROSENZWEIG ,  Nadav SHULMAN ,  Bart PLACKLE

IPC分类号： G06F1/329 ,  G06F9/48

CPC分类号： G06F1/329 ,  G06F9/4893

摘要： Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US20240231470A9

公开(公告)日：2024-07-11

申请号：US18491689

申请日：2023-10-20

申请人： Intel Corporation

发明人： Efraim ROTEM ,  Eliezer WEISSMANN ,  Doron RAJWAN ,  Yoni AIZIK ,  Esfir NATANZON ,  Nir ROSENZWEIG ,  Nadav SHULMAN ,  Bart PLACKLE

IPC分类号： G06F1/329 ,  G06F9/48

CPC分类号： G06F1/329 ,  G06F9/4893

摘要： Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US20230273795A1

公开(公告)日：2023-08-31

申请号：US18311810

申请日：2023-05-03

申请人： Intel Corporation

发明人： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836

摘要： Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20220244996A1

公开(公告)日：2022-08-04

申请号：US17717859

申请日：2022-04-11

申请人： INTEL CORPORATION

发明人： Ankush VARMA ,  Nikhil GUPTA ,  Vasudevan SRINIVASAN ,  Krishnakanth SISTLA ,  Nilanjan PALIT ,  Abhinav KARHU ,  Eugene GORBATOV ,  Eliezer WEISSMANN

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

摘要： An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US20220187893A1

公开(公告)日：2022-06-16

申请号：US17442374

申请日：2020-07-14

申请人： INTEL CORPORATION

发明人： Premanand SAKARDA ,  Efraim ROTEM ,  Eliezer WEISSMANN ,  Hisham ABU SALAH ,  Hadas BEJA ,  Russell FENGER ,  Deepak GANAPATHY ,  James HERMERDING, II ,  Ido KARAVANY ,  Nivedha KRISHNAKUMAR ,  Sudheer NAIR ,  Gilad OLSWANG ,  Moran PERI ,  Avishai WAGNER ,  Zhongsheng WANG ,  Noha YASSIN

IPC分类号： G06F1/324 ,  G06F1/3296

摘要： Described are mechanisms and methods for tracking user behavior profile over large time intervals and extracting observations for a user usage profile. The mechanisms and methods use machine learning (ML) algorithms embedded into a dynamic platform and thermal framework (DPTF) (e.g., Dynamic Tuning Technology) and predict device workloads using hardware (HW) counters. These mechanisms and methods may accordingly increase performance and user responsiveness by dynamically changing an Energy Performance Preference (EPP) based on a longer time workload analysis and workload prediction.

公开(公告)号：US20220179808A1

公开(公告)日：2022-06-09

申请号：US17527929

申请日：2021-11-16

申请人： INTEL CORPORATION

发明人： Eliezer WEISSMANN ,  Efraim ROTEM ,  Doron RAJWAN ,  Hisham ABU SALAH ,  Ariel GUR ,  Guy M. THERIEN ,  Russell J. FENGER

IPC分类号： G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44

摘要： Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.