公开(公告)号：US20230258718A1

公开(公告)日：2023-08-17

申请号：US18308405

申请日：2023-04-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhe Tao ,  Ge Shen ,  Jianlong Cao ,  Ming Wang ,  Rui Fang

IPC: G01R31/3185 ,  G06F9/48

CPC classification number: G01R31/318544 ,  G06F9/4881

Abstract: Embodiments of this application disclose a fault detection method, and relate to the field of computer technologies. The method according to embodiments of this application includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit. By determining the scheduling table of the target task, the test pattern included in the scheduling table is executed, so that execution of all test patterns in a software test library can be avoided. This reduces load of a processor, and effectively improves working efficiency of the processor.

公开(公告)号：US12174254B2

公开(公告)日：2024-12-24

申请号：US18308405

申请日：2023-04-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhe Tao ,  Ge Shen ,  Jianlong Cao ,  Ming Wang ,  Rui Fang

IPC: G01R31/3185 ,  G06F9/48

Abstract: A fault detection method includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit.