Device and method for supporting hybrid automatic repeat request (HARQ)

    公开(公告)号:US12160313B2

    公开(公告)日:2024-12-03

    申请号:US17237867

    申请日:2021-04-22

    Abstract: A transmitting device for supporting Hybrid Automatic Repeat Request (HARQ) includes scrambling and encoding, in which the order of scrambling and encoding is changed compared to the conventional transmitter. Likewise, a receiving device for supporting HARQ includes descrambling and decoding, in which the order of descrambling and decoding is changed compared to the conventional receiver. In particular, the transmitting device is configured to encode at least one data unit using Forward Error Correction (FEC) coding, scramble the encoded data unit based on a scrambling seed, provide an indication of the scrambling seed that is separate from the scrambled and encoded data unit, and transmit the indication of the scrambling seed and then the scrambled and encoded data unit to the receiving device.

    Communication transmitter for retransmitting medium access control (MAC) protocol data unit (MPDU)

    公开(公告)号:US12015489B2

    公开(公告)日:2024-06-18

    申请号:US17521456

    申请日:2021-11-08

    CPC classification number: H04L1/1819 H04L1/08

    Abstract: A communication transmitter retransmits a Medium Access Control (MAC) Protocol Data unit (MPDU) to a communication receiver over a communication channel using a Hybrid Automatic Repeat reQuest (HARQ) retransmission scheme. The MPDU includes a plurality of information bits. The communication transmitter includes a processor configured to determine the MPDU to be retransmitted based on a Block ACK frame received from the communication receiver, the Block ACK frame indicating previously correctly decoded MPDUs at the communication receiver, and to generate a bit sequence to be transmitted to the communication receiver, wherein the bit sequence comprises the plurality of information bits. The communication transmitter further comprises a communication interface configured to transmit the bit sequence to the communication receiver for retransmitting the MPDU to the communication receiver.

    Optimized architecture for a signal decoder

    公开(公告)号:US10771292B2

    公开(公告)日:2020-09-08

    申请号:US16428446

    申请日:2019-05-31

    Abstract: A device for determining a received signal as minimum values of a set of values, the device comprising a processor configured to: load a first set of values in a register; identify a maximum value of the first set of values and a minimum value of the first set of values; in the register, replace the maximum value by a value of a second set of values and simultaneously replace the minimum value by a new value, calculated based on the minimum value, to receive an updated first set of values; and repeat previous steps until all values of the updated first set of values are replaced by values of the second set of values.

    Apparatus and method for deriving a submatrix

    公开(公告)号:US10587318B2

    公开(公告)日:2020-03-10

    申请号:US16014232

    申请日:2018-06-21

    Abstract: An apparatus for deriving a submatrix {tilde over (G)}−1 is described. The apparatus for deriving a submatrix {tilde over (G)}−1 is configured to select an N-elements-column and an N-elements-row of an N×N-Matrix G or G−1. The apparatus for deriving a submatrix {tilde over (G)}−1 is configured to rearrange the selected column to the rightest column and the selected row to the lowest row of G or G−1 so as to generate a N×N-matrix Gp or Gp−1. The apparatus for deriving a submatrix {tilde over (G)}−1 is configured to calculate a submatrix {tilde over (G)}−1 by G ~ - 1 = A - AbcA d - 1 + c T ⁢ Ab , wherein the parameters (N−1)×(N−1)-submatrix A, b, d, c are obtained from the Gp or the Gp−1; wherein G p = [ G ~ b c T d ] , ⁢ G p - 1 = [ A b ~ c ~ T d ~ ] .

    Optimized Architecture for a Signal Decoder
    9.
    发明申请

    公开(公告)号:US20190288883A1

    公开(公告)日:2019-09-19

    申请号:US16428446

    申请日:2019-05-31

    Abstract: A device for determining a received signal as minimum values of a set of values, the device comprising a processor configured to: load a first set of values in a register; identify a maximum value of the first set of values and a minimum value of the first set of values; in the register, replace the maximum value by a value of a second set of values and simultaneously replace the minimum value by a new value, calculated based on the minimum value, to receive an updated first set of values; and repeat previous steps until all values of the updated first set of values are replaced by values of the second set of values.

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