公开(公告)号：US20230044072A1

公开(公告)日：2023-02-09

申请号：US17758142

申请日：2020-01-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Pierre Belgarric ,  Christopher Ian Dalton ,  David Plaquin

IPC: G06F21/55

Abstract: In an example, a method includes providing a computing device with an instruction to cause the computing device to execute the instruction. The method further includes monitoring a side channel of a microarchitectural component of the computing device to obtain an indication of whether or not a state of the microarchitectural component changes as a result of the computing device executing the instruction. The method further includes determining whether or not the indication corresponds to an expected state of the microarchitectural component for the instruction.

公开(公告)号：US20220342992A1

公开(公告)日：2022-10-27

申请号：US17761691

申请日：2019-10-28

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Joshua Serratelli Schiffman ,  Carey Huscroft ,  Pierre Belgarric

IPC: G06F21/57 ,  G06F21/53 ,  G06F21/30

Abstract: The present disclosure relates to methods, devices, and computer-readable media. In an example there is disclosed a method comprising detecting a state of a computing device, the computing device comprising at least one component. The method may further comprise comparing the detected state with a certified state of the device, the certified state indicating an expected state of the device as certified by a trusted authority. The method may further comprise, in response to the detected state and the certified state being different, identifying a component as a source of the difference and checking, by the trusted authority, whether the component is legitimate or not. The method may further still comprise, in response to the component being legitimate, certifying the difference and updating the certified state.

公开(公告)号：US20230141210A1

公开(公告)日：2023-05-11

申请号：US17913606

申请日：2020-04-10

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Pierre Belgarric ,  Christopher Ian Dalton ,  Adrian John Baldwin

IPC: G06N3/04 ,  H04L9/32

CPC classification number: G06N3/04 ,  H04L9/32

Abstract: The present disclosure relates to a neural network. The neural network may comprise a first portion, comprising a plurality of layers of the neural network, to perform a first cryptographic operation on input data. The neural network may further comprise a second portion, comprising a plurality of layers of the neural network, to perform processing on the data. The neural network may further comprise a third portion, comprising a plurality of layers of the neural network, to perform a second cryptographic operation on the processed data.

公开(公告)号：US20220171886A1

公开(公告)日：2022-06-02

申请号：US17415189

申请日：2019-08-20

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Joshua Serratelli Schiffman ,  Carey Huscroft ,  Pierre Belgarric

IPC: G06F21/73 ,  G06F21/44 ,  G06F21/57

Abstract: The disclosure provides a method for verifying authenticity of a component in a product. The method may comprise collecting data relating to a characteristic of the component. The method may further comprise comparing the data to a profile for the component. The profile may comprise an expected characteristic for the component. The method may further comprise determining whether the collected data matches the expected characteristic. The disclosure further provides an apparatus and program.

公开(公告)号：US20240097913A1

公开(公告)日：2024-03-21

申请号：US18452798

申请日：2023-08-21

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Thalia May Laing ,  Maugan Villatel ,  Adrian Shaw ,  Adrian John Baldwin ,  Pierre Belgarric

IPC: H04L9/32

CPC classification number: H04L9/3247

Abstract: In an example, a computing device is described. The computing device comprises a communication interface and a processor. The processor is to determine whether a signature, produced by a signer, is derived from a free state under a stateful signature scheme. The free state is a state that has not been used as an input to generate a signing key. The signature is encrypted by the signer. The processor is further to, in response to determining that the signature is derived from a free state, decrypt the encrypted signature. The processor is further to transmit the decrypted signature to a recipient via the communication interface.

公开(公告)号：US20230176767A1

公开(公告)日：2023-06-08

申请号：US17457564

申请日：2021-12-03

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Adrian John Baldwin ,  Pierre Belgarric ,  Christopher Ian Dalton ,  Thalia May Laing

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: In an example, an apparatus is described. The apparatus comprises a processor to interface with a computing system and a memory device comprising a set of logical cells. A logical cell of the set of logical cells indicates a data value by an amount of charge stored in a physical cell of the logical cell. Charge leakage between the physical cell and an adjacent physical cell of the logical cell is to occur at a rate that at least partially depends on a relative amount of charge stored in the physical cell and the adjacent physical cell. The apparatus further comprises a machine-readable medium storing instructions readable and executable by the processor to cause the processor to process a request issued via the computing system for the processor to cause a memory operation to be performed in the memory device.

公开(公告)号：US20230176746A1

公开(公告)日：2023-06-08

申请号：US17457571

申请日：2021-12-03

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Adrian John Baldwin ,  Pierre Belgarric ,  Christopher Ian Dalton ,  Thalia May Laing

IPC: G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1408

Abstract: In an example, an apparatus is described. The apparatus comprises a memory device comprising a set of logical cells. A logical cell of the set of logical cells indicates a data value by an amount of charge stored in a physical cell of the logical cell. Charge leakage between the physical cell and an adjacent physical cell of the logical cell is to occur at a rate that at least partially depends on a relative amount of charge stored in the physical cell and the adjacent physical cell. A set of data values indicated by the set of logical cells is to change over time due to the charge leakage. The set of data values indicated by the set of logical cells is representative of information that is valid over an estimated period of time, which is based on the rate of charge leakage.

公开(公告)号：US20220109680A1

公开(公告)日：2022-04-07

申请号：US17417129

申请日：2019-06-24

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： David Plaquin ,  Pierre Belgarric ,  Christopher Ian Dalton ,  Titouan Lazard

IPC: G06F21/56

Abstract: In examples, apparatus for detecting malicious or rogue behaviour associated with data packets transmitted between a first device and a second device through a switch is provided, the first device having direct read/write memory access to the second device, in which the apparatus comprises an intercepting device logically intermediate the first device and the switch device to enable the apparatus to analyse the data packets to determine a communication pattern between the first and second devices, compare the communication pattern to a set of expected behaviours for the first device, select, on the basis of the comparison to the set of expected behaviours, a behaviour pattern for the first device, and map the behaviour pattern for the first device to a set of mitigating actions when the behaviour pattern for the first device is symptomatic of a malicious or rogue behaviour.

公开(公告)号：US11288405B2

公开(公告)日：2022-03-29

申请号：US17058152

申请日：2018-10-25

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Pierre Belgarric ,  David Plaquin ,  Eugene Cohen ,  Chris R. Gunning

IPC: G06F21/76 ,  G06F21/60 ,  G06F1/3296 ,  G06K19/073

Abstract: An IC comprising functional circuit to perform primary functions of the IC is provided. The functional circuit is to enable electrical signals to propagate through it within a timing constraint of the functional circuit. The IC comprises at least one canary circuit used for detecting glitch attacks on the circuit. Electrical signals are to propagate through the canary circuit(s) within a defined timing constraint of the canary circuit(s). The canary circuit is to provide a signal path designed such that in the event of a timing constraint of the functional circuit(s) is violated due to a glitch attack, also the timing constraint of the canary circuit(s) is violated.

公开(公告)号：US20210357220A1

公开(公告)日：2021-11-18

申请号：US16606762

申请日：2018-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Pierre Belgarric ,  Christopher l. Dalton ,  David Plaquin ,  Maugan Villatel ,  Joshua Serratelli Schiffman

IPC: G06F9/30

Abstract: Examples include an example computing system comprising a first storage to store executable code, wherein the executable code comprises a plurality of instructions, a second storage to store a first parameter of the executable code, a processing unit to execute each of the instructions of the code, and a monitoring component to, upon execution of each of the instructions of the code by the processing unit, update a second parameter of the code based on that instruction, wherein the monitoring component is to compare the first parameter and the second parameter, and to control execution of further executable code by the processing unit based on the comparison.