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公开(公告)号：US20140085016A1
公开(公告)日：2014-03-27
申请号：US14036736
申请日：2013-09-25
Inventor： Hui Dong LEE , Kwang Chun LEE , Jae Ho JUNG
IPC: H03L7/095
CPC classification number: H03L7/095
Abstract: A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly.
Abstract translation: 公开了一种锁定检测器和包括该锁定检测器的时钟发生器。 锁定检测器包括对第一信号的非匹配部分进行计数的计数器单元和提供计数值的第二信号，第一信号和第二信号是通过将参考信号的相位与 比较信号的相位;以及锁定检测单元，其基于将计数值与参考值进行比较的结果来输出锁定检测信号。 因此，可以快速且精确地检测锁相环的锁定状态。
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公开(公告)号：US20140118045A1
公开(公告)日：2014-05-01
申请号：US14067487
申请日：2013-10-30
Inventor： Hui Dong LEE , Jae Ho JUNG , Kwang Chun LEE
IPC: H03K3/017
CPC classification number: H03K3/017 , H03K5/1565
Abstract: Disclosed is an apparatus for controlling a duty ratio of a signal that includes a clock control unit configured to generate a plurality of control signals based on an input signal, a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other, a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison, and a control voltage generation unit configured to output a delay control voltage.
Abstract translation: 公开了一种用于控制信号的占空比的装置，其包括被配置为基于输入信号生成多个控制信号的时钟控制单元，半周生成单元，被配置为通过使用输入信号生成相乘的信号 以及延迟信号，其通过基于延迟控制电压延迟所述输入信号而获得，并且将所述相乘的信号除以产生彼此成反比的第一除法信号和第二除法信号，所述比较器单元被配置为比较 基于由时钟控制单元提供的控制信号的具有第二分频信号的脉冲宽度的第一分频信号的脉冲宽度，并输出与比较结果相对应的延迟控制信号，以及控制电压生成单元配置 输出延迟控制电压。
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公开(公告)号：US20160218428A1
公开(公告)日：2016-07-28
申请号：US14993502
申请日：2016-01-12
Inventor： Jae Ho JUNG , Heon Kook KWON , Bong Hyuk PARK
IPC: H01Q3/26
CPC classification number: H01Q3/267 , H04B17/0085 , H04B17/12 , H04B17/14 , H04B17/21
Abstract: An error calibrating apparatus of an array antenna system according to an exemplary embodiment of the present invention is an error calibrating apparatus of an array transmitting antenna system having a plurality of array antennas and includes a calibrating signal generator which generates an error calibrating signal as a single frequency signal, in an area which does not interfere with a passband of a transmitted signal; an array RF transmitter which upwardly converts the transmitted signal into an RF band to transmit the signal to the plurality of array antennas; an error calibration estimator which correlates the error calibrating signal and the receiving single frequency signal received by passing through the array RF transmitter to estimate a transfer function of the array RF transmitter and extract a filter coefficient using the estimated transfer function; and a complex filter which calibrates an error of the transmitted signal by applying the filter coefficient to output the corrected transmitted signal to the array RF transmitter.
Abstract translation: 根据本发明的示例性实施例的阵列天线系统的误差校准装置是具有多个阵列天线的阵列发射天线系统的误差校准装置，并且包括校准信号发生器，该校准信号发生器产生作为单个的误差校准信号 在不干扰发送信号的通带的区域中的频率信号; 阵列RF发射器，其将所发射的信号向上转换成RF频带，以将信号传输到多个阵列天线; 误差校准估计器，其通过通过阵列RF发射器接收的误差校准信号和接收单频信号相关，以估计阵列RF发射机的传递函数，并使用估计的传递函数提取滤波器系数; 以及复数滤波器，其通过应用滤波器系数校正发射信号的误差，以将校正的发射信号输出到阵列RF发射机。
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4.发明申请SECOND ORDER LOOP FILTER AND MULTI-ORDER DELTA SIGMA MODULATOR INCLUDING THE SAME 有权第二订单循环滤波器和包括其中的多阶段三角形调制器公开(公告)号：US20150229292A1
公开(公告)日：2015-08-13
申请号：US14617705
申请日：2015-02-09
Inventor： Young Kyun CHO , Jae Ho JUNG , Kwangchun LEE
CPC classification number: H03M3/43 , H03H11/1247 , H03H11/126 , H03H11/1291 , H03H11/32 , H03M3/38 , H03M3/422 , H03M3/454 , H03M3/458
Abstract: Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a differential input of the first input, and an output; an inverter inverting a signal output from the output of the operational amplifier to output an inverted signal; a first resistor connected to between the first input and a first node; a second resistor connected to between the output of the operational amplifier and the first node; a third resistor connected to between the first input and an input signal; a first capacitor connected to between the second input and the first node; a second capacitor connected to between the output of the operational amplifier and an output of the inverter; and a third capacitor connected to between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage.
Abstract translation: 提供了二阶环路滤波器（LF）。 第二级LF包括：运算放大器，包括第一输入端，接收第一输入端的差分输入端的第二输入端和输出端; 逆变器，反相从运算放大器的输出端输出的信号，输出反相信号; 连接到第一输入和第一节点之间的第一电阻器; 连接到运算放大器的输出端和第一节点之间的第二电阻器; 连接到所述第一输入端和输入信号之间的第三电阻器; 连接到所述第二输入端和所述第一节点之间的第一电容器; 连接在运算放大器的输出端和反相器的输出端之间的第二电容器; 以及连接到所述运算放大器的输出和第一输入之间的第三电容器，其中所述第二输入端连接到接地电压。
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5.发明申请公开(公告)号：US20150200589A1
公开(公告)日：2015-07-16
申请号：US14311417
申请日：2014-06-23
Inventor： Hui Dong LEE , Jae Ho JUNG , Kwangchun LEE
CPC classification number: H02M3/07 , H03L7/0895 , H03L7/0896 , H03L7/0898
Abstract: Provided is a charge pump circuit having a current mirror structure, including a first voltage controller including a plurality of first resistors and a plurality of first switches, and in response to a switching control signal corresponding to a bias current, driving the plurality of first switches to allow a current path passing through the plurality of first resistors to bypass, thereby controlling a voltage level of an output end, a second voltage controller including a plurality of second resistors and a plurality of second switches, and in response to the switching control signal, driving the plurality of second switches to allow a current path passing through the plurality of second resistors to bypass, thereby controlling a voltage level of an output end to correspond to the voltage of the output end of the first voltage controller.
Abstract translation: 提供了具有电流镜结构的电荷泵电路，包括包括多个第一电阻器和多个第一开关的第一电压控制器，并且响应于与偏置电流相对应的开关控制信号，驱动多个第一开关 允许通过多个第一电阻器的电流路径旁路，从而控制输出端的电压电平，包括多个第二电阻器和多个第二开关的第二电压控制器，并且响应于开关控制信号 驱动所述多个第二开关以允许通过所述多个第二电阻器的电流路径旁路，由此控制输出端的电压电平对应于所述第一电压控制器的输出端的电压。
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Patent Agency Ranking
6.发明申请METHOD OF GENERATING DRIVING SIGNAL FOR DRIVING DUAL MODE SUPPLY MODULATOR FOR POWER AMPLIFIER AND DEVICE THEREOF 有权产生用于驱动功率放大器的双模式供电调制器的驱动信号的方法及其装置公开(公告)号：US20150071371A1
公开(公告)日：2015-03-12
申请号：US14267262
申请日：2014-05-01
Inventor： Sung Jun LEE , Jae Ho JUNG , Kwangchun LEE
IPC: H04L25/49
CPC classification number: H03F3/245 , H03F1/025 , H03F3/195 , H03F2200/102 , H03F2200/331 , H03F2200/336 , H03F2200/511 , H03F2200/78 , H03M7/3004
Abstract: Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.
Abstract translation: 提供了一种产生用于驱动功率放大器的双模式电源调制器的驱动信号的方法。 该方法包括当复数信号的当前包络是预设阈值或更大时获得要发送的复基带信号的包络，将复数信号的包络与预设阈值进行比较，或者当具有 在先前的N比较中预设的阈值或更大，通过数模转换器输出配置有第一逻辑电平的数字板输出信号; 并且当复信号的当前包络小于预设阈值时，并且当在先前N次比较中没有具有预设阈值或更大值的结果时，通过数字信号输出配置有第二逻辑电平的数字板输出信号 模拟转换器。
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公开(公告)号：US20130147462A1
公开(公告)日：2013-06-13
申请号：US13687200
申请日：2012-11-28
Inventor： Hui Dong LEE , Jae Ho JUNG
IPC: G01R23/00
CPC classification number: G01R23/00 , G01R23/005
Abstract: A frequency comparator outputs an input reference signal and a comparison target signal as pulse-form signals, and is charged or discharged with a voltage corresponding to the reference signal to output a reference voltage having a variable first frequency range, and charged or discharged with a voltage corresponding to the comparison target signal to output a comparison target voltage having a variable second frequency range. The frequency comparator compares the reference voltage having the first frequency range and the comparison output voltage having the second frequency range.
Abstract translation: 频率比较器输出输入参考信号和比较目标信号作为脉冲形式的信号，并用对应于参考信号的电压进行充电或放电，以输出具有可变的第一频率范围的参考电压，并用 电压，以输出具有可变的第二频率范围的比较目标电压。 频率比较器比较具有第一频率范围的参考电压和具有第二频率范围的比较输出电压。
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公开(公告)号：US20190327070A1
公开(公告)日：2019-10-24
申请号：US16393616
申请日：2019-04-24
Inventor： Jae Ho JUNG , Kwang Seon KIM
Abstract: Disclosed are a method and apparatus for canceling self-interference signals in a communication system. A first communication node includes a signal transmission unit configured to generate a first RF signal, an antenna module configured to transmit the first RF signal generated by the signal transmission unit and receive a second RF signal from a second communication node, a signal reception unit configured to process the second RF signal and a self-interference signal caused by the first RF signal, and an SIC circuit configured to cancel the self-interference signal. The SIC circuit includes a DSIC circuit for canceling the self-interference signal in a digital domain and an ASIC circuit and an HSIC circuit for canceling the self-interference signal in an analog domain. Accordingly, the performance of the communication system may be enhanced.
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公开(公告)号：US20140064355A1
公开(公告)日：2014-03-06
申请号：US14011268
申请日：2013-08-27
Inventor： Young Kyun CHO , Sung Jun LEE , Seung Hyun JANG , Bong Hyuk PARK , Jae Ho JUNG , Kwang Chun LEE
CPC classification number: H04L25/4902 , H03K7/08 , H03M3/504 , H04B14/062
Abstract: A delta-sigma modulator and a transmitter apparatus including the same are disclosed. The delta-sigma modulator includes a first integrator, a second integrator, a first comparator configured to compare an output signal of the second integrator and a reference signal, and output a first comparison signal, a second comparator configured to compare the output signal of the second integrator and the reference signal, and output a second comparison signal, a first DAC configured to output the first signal corresponding to the first comparison signal and the second comparison signal, a second DAC configured to output the second signal corresponding to the first comparison signal and the second comparison signal, a delayer configured to generate a delayed signal that delays the first comparison signal and the second comparison signal by a predetermined time, and an output DAC configured to generate an output signal having a multi-level corresponding to the delayed signal.
Abstract translation: 公开了一种Δ-Σ调制器及其发射机装置。 Δ-Σ调制器包括第一积分器，第二积分器，被配置为比较第二积分器的输出信号和参考信号的第一比较器，并输出第一比较信号;第二比较器，被配置为比较第二积分器的输出信号 第二积分器和参考信号，并输出第二比较信号，第一DAC被配置为输出对应于第一比较信号和第二比较信号的第一信号;第二DAC，被配置为输出对应于第一比较信号的第二信号 和第二比较信号，延迟器，被配置为产生将第一比较信号和第二比较信号延迟预定时间的延迟信号;以及输出DAC，被配置为产生具有与延迟信号相对应的多电平的输出信号 。
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公开(公告)号：US20210159794A1
公开(公告)日：2021-05-27
申请号：US16902349
申请日：2020-06-16
Inventor： Young Kyun CHO , Heon Kook KWON , Kwang Seon KIM , Tae Joong KIM , Kwangchun LEE , Jung Nam LEE , Jae Ho JUNG
IPC: H02M3/158
Abstract: A direct current-to-direct current (DC-DC) converter providing multiple operation modes includes a buck power stage configured to lower an input voltage, a boost power stage configured to increase the input voltage, and a multi-mode controller configured to control the buck power stage and the boost power stage, wherein the multi-mode controller is configured to generate a signal to control the buck power stage and the boost power stage according to the input voltage and an output voltage, and control the buck power stage and the boost power stage using the signal.
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